18-11
JTAG TEST-LOGIC UNIT
Typically, you would use the SAMPLE/PRELOAD instruction to load data onto the boundary-
scan register’s latched parallel outputs before loading the EXTEST instruction. You load the EX-
TEST instruction by manipulating TDI to supply the binary opcode (0000). The Update-DR state
drives the preloaded data onto the pins for the first test. Stimuli for the remaining tests are shifted
in while the results for the completed tests are shifted out.
18.3.5 Disabling the Output Drivers
The HIGHZ instruction places all system logic outputs into an inactive drive (high impedance)
state. This state allows an in-circuit emulator to drive signals onto connections that processor out-
puts normally drive, without risk of damaging the processor. It also allows you to connect a data
source (such as a test chip) to board-level signals (such as an array of memory devices) that the
processor outputs normally drive. During normal operation, the processor outputs would be ac-
tive, while the test chip outputs would be inactive. During testing, you would use the HIGHZ in-
struction to place the processor outputs into an inactive drive state, then enable the test chip to
drive the connections.
You load the HIGHZ instruction by manipulating the TDI input to supply the binary opcode
(1000). The Capture-DR state loads a logic 0 into the bypass register, and the Shift-DR state shifts
the value out.
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