Intel 386 - Dmachr; D.10 Dmachr

D-15
SYSTEM REGISTER QUICK REFERENCE
D.10 DMACHR
DMA Chaining
DMACHR
(write only)
Expanded Addr:
ISA Addr:
Reset State:
F019H
—
00H
7 0
———— —CE0CS
Bit
Number
Bit
Mnemonic
Function
7–3 — Reserved; for compatibility with future devices, write zeros to these bits.
2 CE Chaining Enable:
0 = Disables the chaining buffer-transfer mode for the channel specified
by bit 0.
1 = Enables the chaining buffer-transfer mode for the channel specified
by bit 0.
1 0 Must be 0 for correct operation.
0 CS Channel Select:
0 = The selection for bit 2 affects channel 0.
1 = The selection for bit 2 affects channel 1.