Intel 386

13-3
SYNCHRONOUS SERIAL I/O UNIT
Figure 13-3. Transmitter in Slave Mode, Receiver in Master Mode
Figure 13-4. Transmitter and Receiver in Slave Mode
Receiver
Transmitter
Baud-rate
Generator

A2436-02
SRXCLK
(pin mux)
SSIOTX
(pin mux)
SSIORX
Clock Source
(PSCLK or SERCLK)
STXCLK
SSTBE
(to DMA controller)
SSRBF
(to DMA controller)
SSIOINT
(to Slave interrupt
controller IR1)
SSIOCON.5 (TIE)
SSIOCON.1 (RIE)
S
y
s
t
e
m

B
u
s
Receiver
Transmitter

A2437-02
SSIOTX
(pin mux)
SSIORX
STXCLK
SRXCLK
(pin mux)
SSTBE
(to DMA controller)
SSRBF
(to DMA controller)
SSIOINT
(to Slave interrupt
controller IR1)
SSIOCON.5 (TIE)
SSIOCON.1 (RIE)
S
y
s
t
e
m

B
u
s