Intel 386 User Manual

14-11
CHIP-SELECT UNIT
14.3.3 Bus Cycle Length Control
Each chip-select channel controls how bus cycles to its address block terminate. Each channel can
generate up to 31 wait states and then unconditionally terminate or wait for an external bus ready
signal to terminate. If the channel is programmed for wait states and to sample external READY#,
the external READY# is ignored until the programmed number of wait states has been inserted
into the cycle. If greater than 31 wait states are required, ready must be generated externally, and
the external READY# option must be selected.
NOTE
When a chip-select region overlaps on-chip peripheral addresses, the on-chip
peripheral always generates READY# and overrides the channel’s
configuration.
14.3.4 Bus Size Control
The processor assumes that the currently addressed device requires a 16-bit data bus unless the
bus size control pin (BS8#) is asserted. When asserted, BS8# tells the processor that the addressed
device requires an 8-bit data bus. You can program a chip-select channel specifically for 8-bit de-
vices. This causes the CSU to assert BS8# automatically each time it activates the channel.
14.3.5 Overlapping Regions
You can configure CSU channels to have overlapping address blocks. When channels with over-
lapping address blocks have different bus cycle length and bus size configurations, the CSU must
adjust these parameters. Figure 14-3 shows how the CSU adjusts the bus cycle length. In the case
of different bus sizes, the CSU defaults to an 8-bit bus size.
If one overlapping chip-select region has the RDY bit set and the other overlapping region does
not, the CSU defaults to the ‘RDY Bit Set’ operation; in this case an external READY# is neces-
sary to terminate accesses to the address locations in which the two chip-selects overlap.
NOTE
If a bus cycle address activates multiple overlapping CSU channels, all the
enabled chip-select signals of those channels go active. To avoid contention on
the data bus, care must be taken when using these chip-select signals
externally.

Intel 386 Specifications

General

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm