Intel 386 User Manual

5-35
DEVICE CONFIGURATION
Table 5-10. DMACFG Register Design Worksheet
Bit # DMACFG Value
7 0 = Enables DACK1# at chip pin
1 = Disables DACK1# at chip pin
6–4 000 = DRQ1 pin (external peripheral) connected to DREQ1
001 = SIO channel 1’s receive buffer full signal (RBFDMA1) connected to DREQ1
010 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) to DREQ1
011 =SSIO receive holding buffer full signal (SSRBF) to DREQ1
100 = TCU counter 2’s output signal (OUT2) to DREQ1
101 = SIO channel 0’s receive buffer full signal (RBFDMA0) to DREQ1
110 = SIO channel 1’s transmit buffer empty signal (TXEDMA1) to DREQ1
111 = SSIO transmit holding buffer empty signal (SSTBE) to DREQ1
3 0 = Enables DACK0# at chip pin
1 = Disables DACK0# at chip pin
2–0 000 = DRQ0 pin (external peripheral) connected to DREQ0
001 = SIO channel 0’s receive buffer full signal (RBFDMA0) connected to DREQ0
010 = SIO channel 1’s transmit buffer empty signal (TXEDMA1) connected to DREQ0
011 = SSIO transmit holding buffer empty signal (THBE) connected to DREQ0
100 = TCU counter 1’s output signal (OUT1) connected to DREQ0
101 = SIO channel 1’s receive buffer full signal (RBFDMA1) connected to DREQ0
110 = SIO channel 0’s transmit buffer empty signal (TXEDMA0) connected to DREQ0
111 = SSIO receive holding buffer full signal (RHBF) connected to DREQ0

Intel 386 Specifications

General

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm