Intel 386 User Manual

6-41
BUS INTERFACE UNIT
Also, bit 5 in the PINCFG register (Figure 5-15 on page 5-24) must be cleared, to connect the
coprocessor-related signals of the core to the package pins.
Below is an example of a simple routine that can be executed using the math-coprocessor:
6.6.2 SRAM/FLASH Interface
SRAM and FLASH devices can be connected directly to the Intel386 EX processor as shown in
Figure 6-16. Separate CSn#, RD# and WR# strobes enable a “glueless” interface. The WR# sig-
nal, when used with an “EARLY READY#” (described in “Write Cycle” on page 6-16), guaran-
tees the ‘WE#-Inactive-to-Address-Invalid’ time of most SRAM and FLASH devices.
Figure 6-16. Intel386 EX Processor to SRAM/FLASH Interface
fninit ;; Initialize Math Coprocessor
fldpi ;; Load (Push on to the 387 stack) “Pi”
fld1 ;; Load (Push on to the 387 stack) “1”
fadd ;; Add the two values, i.e. Pi + 1
fist word ptr [di] ;; Convert to integer and Store at
;; location pointed to by DS:DI
Intel386™ EX
Embedded
Processor
OE#

CE#

WE#
A2853-02
SRAM
or FLASH
Address
Data
RD#

CS
n #

WR#

Intel 386 Specifications

General

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm