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Intel 386 User Manual
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6
-29
BUS I
NTERF
ACE UNI
T
Figure 6-1
1. Basic Refr
esh Cycle
A2491-02
LOCK#
D15:0
CLK2
BHE#, BLE#
M/IO#, D/C#
Valid 1
RD#
READY#
Ti
T1
T2
Ti
T1
T2
T2
Ti
Ti
T1
Cycle 1
Nonpipelined
External
(Read)
Cycle 2
Refresh
CLKOUT
Idle
Idle
Cycle 3
Nonpipelined
External
(Write)
[Late Ready]
T2
Valid 3
ADS#
NA#
A25:1
W/R#
WR#
LBA#
Idle
REFRESH#
Float
HOLD
HLDA
In
Out
Valid 1
Valid 2
Valid 1
Valid 2
Valid 3
141
143
Table of Contents
Table of Contents
4
Guide to this Manual
26
Manual Contents
28
Notational Conventions
30
Special Terminology
31
Related Documents
32
Electronic Support Systems
33
Faxback Service
33
Bulletin Board System (BBS)
34
Compuserve Forums
34
Technical Support
34
World Wide Web
34
Product Literature
35
Architectural Overview
36
Intel386 EX EMBEDDED PROCESSOR CORE
38
Intel386™ EX Embedded Processor Block Diagram
39
Integrated Peripherals
40
PC-Compatible Peripherals
40
Embedded Application-Specific Peripherals
41
Core Overview
42
Additional Address Lines
44
Intel386 CX PROCESSOR ENHANCEMENTS
44
System Management Mode
44
Instruction Pipelining
45
Intel386 CX PROCESSOR INTERNAL ARCHITECTURE
45
The Intel386™ CX Processor Internal Block Diagram
46
Core Bus Unit
47
Instruction Decode Unit
47
Instruction Prefetch Unit
47
Execution Unit
48
Paging Unit
48
Segmentation Unit
48
CORE Intel386 EX PROCESSOR INTERFACE
49
System Register Organization
50
Overview
52
I/O Address Space for Pc/At Systems
53
Intel386 EX Processor Peripheral Registers
53
Intel386 Processor Core Architecture Registers
53
Expanded I/O Address Space
54
PC/AT I/O Address Space (10-Bit Decode)
54
Expanded I/O Address Space (16-Bit Decode)
55
Organization of Peripheral Registers
56
Peripheral Register I/O Address Map in Slot 15
56
Address Configuration Register
57
I/O Address Decoding Techniques
57
Address Configuration Register (REMAPCFG)
58
Enabling and Disabling the Expanded I/O Space
59
Programming REMAPCFG Example
59
Setting the ESE Bit Code Example
59
Addressing Modes
60
DOS-Compatible Mode
60
DOS-Compatible Mode
61
Enhanced DOS Mode
62
Non-DOS Mode
62
Nonintrusive DOS Mode
62
Example of Nonintrusive DOS-Compatible Mode
63
Enhanced DOS Mode
64
Nondos Mode
65
Peripheral Register Addresses
66
Device Configuration
72
Introduction
74
Peripheral and Pin Connections
75
DMA Controller, Bus Arbiter, and Refresh Unit Configuration
76
DMA Service to an SIO or SSIO Peripheral
76
Peripheral Configuration
76
Using the DMA Unit with External Devices
76
Limitations Due to Pin Signal Multiplexing
77
Using the Timer to Initiate DMA Transfers
77
Configuration of DMA, Bus Arbiter, and Refresh Unit
78
DMA Configuration Register (DMACFG)
79
Interrupt Control Unit Configuration
80
Master's IR3 Connections
81
Master's IR4 Connections
81
Interrupt Control Unit Configuration
82
Interrupt Configuration Register (INTCFG)
83
Timer/Counter Unit Configuration
84
Timer/Counter Unit Configuration
85
Timer Configuration Register (TMRCFG)
86
Asynchronous Serial I/O Configuration
87
Serial I/O Unit 0 Configuration
88
Serial I/O Unit 1 Configuration
89
SIO and SSIO Configuration Register (SIOCFG)
90
SSIO Unit Configuration
91
Synchronous Serial I/O Configuration
91
Chip-Select Unit and Clock and Power Management Unit Configuration
92
Configuration of Chip-Select Unit and Clock and Power Management Unit
93
Core Configuration
94
Port 92 Configuration Register (PORT92)
95
Pin Configuration
96
Signal Pairs on Pins Without a Multiplexer
96
Pin Configuration Register (PINCFG)
97
Port 1 Configuration Register (P1CFG)
98
Port 2 Configuration Register (P2CFG)
99
Port 3 Configuration Register (P3CFG)
100
Configuration Example
101
Device Configuration Procedure
101
Example Design Requirements
101
Example Design Solution
102
Example Pin Configuration Registers
103
Example DMACFG Configuration Register
104
Example TMRCFG Configuration Register
105
Example INTCFG Configuration Register
106
Example SIOCFG Configuration Register
106
Pin Configuration Register Design Woksheet
107
DMACFG Register Design Worksheet
108
TMRCFG Register Design Worksheet
109
INTCFG Register Design Worksheet
110
SIOCFG Register Design Worksheet
110
Bus Interface Unit
112
Overview
114
Bus Interface Unit Signals
116
Bus Signal Descriptions
116
Bus Operation
118
Bus Status Definitions
118
Basic External Bus Cycles
119
Bus States
120
Pipelining
121
Data Bus Transfers and Operand Alignment
122
Ready Logic
123
Sequence of Nonaligned Bus Transfers
123
Ready Logic
124
Basic Internal and External Bus Cycles
125
Bus Cycles
126
Read Cycle
126
Nonpipelined Address Read Cycles
128
Write Cycle
129
Nonpipelined Address Write Cycles
131
Pipelined Cycle
132
Complete Bus States (Including Pipelined Address)
133
Pipelined Address Cycles
134
Interrupt Acknowledge Cycle
136
Interrupt Acknowledge Cycles
138
Halt/Shutdown Cycle
139
Halt Cycle
140
Refresh Cycle
141
Basic Refresh Cycle
142
Refresh Cycle During HOLD/HLDA
143
BS8 Cycle
144
Read Cycles
144
Write Cycles
144
Bit Cycles to 8-Bit Devices (Using BS8#)
146
Bus Lock
147
Locked Cycle Activators
147
Locked Cycle Timing
147
External Bus Master Support (Using Hold, Hlda)
148
LOCK# Signal Duration
148
LOCK# Signal During Address Pipelining
148
HOLD/HLDA Timing
149
HOLD Signal Latency
150
Design Considerations
151
Interface to Intel387™ SX Math Coprocessor
151
Intel386 EX Processor to Intel387 SX Math Coprocessor Interface
152
System Configuration
152
Software Considerations
153
Intel386 EX Processor to SRAM/FLASH Interface
154
SRAM/FLASH Interface
154
Intel386 EX Processor to PSRAM Interface
155
PSRAM Interface
155
Intel386 EX Processor to Paged DRAM Interface
156
Paged DRAM Interface
156
Intel386 EX Processor and Non-Paged DRAM Interface
157
Non-Paged DRAM Interface
157
System Management Mode
158
Smm Hardware Interface
160
System Management Interrupt Input (SMI#)
160
System Management Mode Overview
160
SMM Active Output (SMIACT#)
161
System Management RAM (SMRAM)
161
CR0 Bits Cleared Upon Entering SMM
162
Register Status During SMM
162
System Management Mode Programming and Configuration
162
SMM Processor State Initialization Values
163
System Management Interrupt
163
Standard SMI#
164
SMIACT# Latency
165
Relative Priority of Exceptions and Interrupts
166
SMI# Priority
166
SMI# During HALT
167
System Management Interrupt During HALT Cycle
167
HALT Restart
168
SMI# During I/O Instruction
168
System Management Interrupt During I/O Instruction
168
I/O Restart
169
Interrupt During SMM Handler
169
SMI# Timing
169
SMM Handler Interruption
169
HALT During SMM Handler
170
Interrupted SMI# Service
170
Chip-Select Unit Support for SMRAM
171
HALT During SMM Handler
171
Idle Mode and Powerdown Mode During SMM
171
SMI# During SMM Operation
171
SMRAM Programming
171
SMRAM State Dump Area
173
Resume Instruction (RSM)
174
THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS
174
Programming Considerations
175
System Management Mode Code Example
175
Clock and Power Management Unit
180
Clock Generation Logic
182
Overview
182
Clock and Power Management Unit Connections
183
Clock Synchronization
184
Power Management Logic
184
SMM Interaction with Power Management Modes
185
Bus Interface Unit Operation During Idle Mode
186
SMM Interaction with Idle and Powerdown Modes
186
Watchdog Timer Unit Operation During Idle Mode
186
Clock and Power Management Registers and Signals
187
Clock and Power Management Signals
187
Clock Prescale Register (CLKPRS)
188
Controlling the Psclk Frequency
188
Controlling Power Management Modes
189
Power Control Register (PWRCON)
189
Idle Mode
190
Timing Diagram, Entering and Leaving Idle Mode
190
Powerdown Mode
191
Ready Generation During HALT
191
Design Considerations
192
Reset Considerations
192
Timing Diagram, Entering and Leaving Powerdown Mode
192
Built-In Self Test
193
JTAG Reset
193
Power-Up Considerations
193
Reset Synchronization Circuit
193
Clock and Power Management Unit Code Example
194
Powerdown Mode and Idle Mode Considerations
194
Programming Considerations
194
Interrupt Control Unit
198
Overview
200
Interrupt Control Unit Configuration
202
Icu Operation
203
Interrupt Sources
203
C59A Master and Slave Interrupt Sources
204
Assigning an Interrupt Level
205
Interrupt Priority
205
Determining Priority
206
Methods for Changing the Default Interrupt Structure
206
Interrupt Vectors
207
Interrupt Process
208
Interrupt Process – Master Request from Non-Slave Source
210
Interrupt Process – Slave Request
211
Interrupt Process – Master Request from Slave Source
212
Poll Mode
213
Register Definitions
214
ICU Registers
215
Port 3 Configuration Register (P3CFG)
217
Interrupt Configuration Register (INTCFG)
218
Initialization Command Word 1 (ICW1)
219
Initialization Command Word 1 Register (ICW1)
219
Initialization Command Word 2 (ICW2)
220
Initialization Command Word 2 Register (ICW2)
220
Initialization Command Word 3 (ICW3)
221
Initialization Command Word 3 Register (ICW3 – Master)
221
Initialization Command Word 3 Register (ICW3 – Slave)
222
Initialization Command Word 4 (ICW4)
223
Initialization Command Word 4 Register (ICW4)
223
Operation Command Word 1 (OCW1)
224
Operation Command Word 2 (OCW2)
225
Operation Command Word 3 (OCW3)
226
In-Service Register (ISR)
227
Interrupt Request Register (IRR)
227
Poll Status Byte (POLL)
227
Design Considerations
228
Interrupt Acknowledge Cycle
228
Interrupt Detection
228
Cascading Interrupt Controllers
229
Spurious Interrupts
229
Cascading External 82C59A Interrupt Controllers
230
Interrupt Control Unit Code Examples
231
Programming Considerations
231
Timer/Counter Unit
242
Overview
244
Timer/Counter Unit Signal Connections
245
TCU Signals and Registers
246
TCU Associated Registers
247
Tcu Operation
248
Mode 0 - Interrupt on Terminal Count
249
Operations Caused by GATE N
249
Mode 0 – Basic Operation
250
Mode 0 – Disabling the Count
250
Mode 0 – Writing a New Count
251
Mode 1 - Hardware Retriggerable One-Shot
251
Mode 1 – Basic Operation
252
Mode 1 – Retriggering the One-Shot
252
Mode 1 – Writing a New Count
253
Mode 2 - Rate Generator
253
Mode 2 – Basic Operation
254
Mode 2 – Disabling the Count
254
Mode 2 – Writing a New Count
255
Mode 3 - Square Wave
255
Mode 3 – Basic Operation (Even Count)
256
Mode 3 – Basic Operation (Odd Count)
257
Mode 3 – Disabling the Count
257
Mode 3 – Writing a New Count (Without a Trigger)
258
Mode 4 - Software-Triggered Strobe
259
Mode 4 – Basic Operation
259
Mode 4 – Disabling the Count
260
Mode 4 – Writing a New Count
260
Mode 5 - Hardware-Triggered Strobe
261
Mode 5 – Basic Operation
261
Mode 5 – Retriggering the Strobe
262
Mode 5 – Writing a New Count Value
262
Configuring the Input and Output Signals
263
GATE N Connection Options
263
Hardware Control of GATE N
263
Register Definitions
263
Software Control of GATE N
263
Timer Configuration Register (TMRCFG)
264
Port 3 Configuration Register (P3CFG)
265
Pin Configuration Register (PINCFG)
266
Initializing the Counters
267
Timer Control Register (TMRCON – Control Word Format)
268
Minimum and Maximum Initial Counts
269
Timer N Register (TMR N – Write Format)
269
Writing the Counters
269
Counter-Latch Command
270
Reading the Counter
270
Simple Read
270
Timer Control Register (TMRCON – Counter-Latch Format)
271
Timer N Register (TMR N – Read Format)
272
Read-Back Command
273
Timer Control Register (TMRCON – Read-Back Format)
273
Timer N Register (TMR N – Status Format)
275
Programming Considerations
276
Results of Multiple Read-Back Commands Without Reads
276
Timer/Counter Unit Code Examples
277
Asynchronous Serial I/O Unit
286
Overview
288
Serial I/O Unit 1 Configuration
289
SIO Signals
290
Baud-Rate Generator
291
SIO N Baud-Rate Generator Clock Sources
291
Sio Operation
291
Divisor Values for Common Bit Rates
292
Maximum and Minimum Output Bit Rates
292
SIO N Transmitter
293
SIO N Transmitter
294
SIO N Data Transmission Process Flow
295
SIO N Receiver
296
SIO N Data Reception Process Flow
298
Diagnostic Mode
299
Modem Control
299
SIO DMA Sources
300
SIO Interrupt and DMA Sources
300
SIO Interrupt Sources
300
Status Signal Priorities and Sources
300
External UART Support
301
Register Definitions
302
SIO Registers
302
Access to Multiplexed Registers
303
Pin and Port Configuration Registers (PINCFG and P N CFG [ N = 1-3])
304
Pin Configuration Register (PINCFG)
304
Port 1 Configuration Register (P1CFG)
305
Port 2 Configuration Register (P2CFG)
306
Port 3 Configuration Register (P3CFG)
307
SIO and SSIO Configuration Register (SIOCFG)
308
Divisor Latch Registers (DLL N and DLH N )
309
Transmit Buffer Register (TBR N )
310
Receive Buffer Register (RBR N )
311
Serial Line Control Register (LCR N )
312
Serial Line Status Register (LSR N )
313
Interrupt Enable Register (IER N )
314
Interrupt ID Register (IIR N )
315
Modem Control Register (MCR N )
316
Modem Control Signals – Diagnostic Mode Connections
316
Modem Control Signals – Internal Connections
316
Modem Control Register (MCR N )
317
Modem Status Register (MSR N )
318
Programming Considerations
319
Scratch Pad Register (SCR N )
319
Asynchronous Serial I/O Unit Code Examples
320
Dma Controller
334
Overview
336
DMA Unit Block Diagram
337
DMA Terminology
338
DMA Signals
339
Bus Cycle Options for Data Transfers
340
Dma Operation
340
DMA Transfers
340
Fly-By Mode
340
Operations Performed During Transfer
341
Programmable DMA Transfer Direction
341
Two-Cycle Mode
341
DMA Usage of the 4-Byte Temporary Register
342
Ready Generation for DMA Cycles
342
DMA Temporary Buffer Operation for a Read Transfer
343
DMA Temporary Buffer Operation for a Write Transfer
343
Bus Control Arbitration
344
Start of a Two-Cycle DMA Transfer Initiated by DRQ N
344
Starting DMA Transfers
344
Changing the Priority of the DMA Channel and External Bus Requests
345
Ending DMA Transfers
345
Buffer Transfer Ended by an Expired Byte Count
346
Buffer Transfer Ended by the EOP# Input
346
Autoinitialize Buffer-Transfer Mode
347
Buffer-Transfer Modes
347
Chaining Buffer-Transfer Mode
347
Single Buffer-Transfer Mode
347
Data-Transfer Modes
348
Single Data-Transfer Mode
349
Single Data-Transfer Mode with Single Buffer-Transfer Mode
350
Single Data-Transfer Mode with Autoinitialize Buffer-Transfer Mode
351
Single Data-Transfer Mode with Chaining Buffer-Transfer Mode
352
Block Data-Transfer Mode
353
Block Data-Transfer Mode with Single Buffer-Transfer Mode
354
Block Data-Transfer Mode with Autoinitialize Buffer-Transfer Mode
355
Buffer Transfer Suspended by the Deactivation of DRQ N
356
Demand Data-Transfer Mode
356
Demand Data-Transfer Mode with Single Buffer-Transfer Mode
357
Demand Data-Transfer Mode with Autoinitialize Buffer-Transfer Mode
358
Demand Data-Transfer Mode with Chaining Buffer-Transfer Mode
359
Cascade Mode
360
Cascade Mode
361
DMA Interrupts
361
8237A Compatibility
362
DMA Registers
363
Register Definitions
363
Pin Configuration Register (PINCFG)
366
DMA Configuration Register (DMACFG)
367
Channel Registers
368
DMA Overflow Enable Register (DMAOVFE)
369
Overflow Enable Register (DMAOVFE)
369
Command 1 Register (DMACMD1)
370
DMA Command 1 Register (DMACMD1)
370
DMA Status Register (DMASTS)
371
Status Register (DMASTS)
371
Command 2 Register (DMACMD2)
372
DMA Command 2 Register (DMACMD2)
372
Mode 1 Register (DMAMOD1)
373
DMA Mode 1 Register (DMAMOD1)
374
Mode 2 Register (DMAMOD2)
375
DMA Mode 2 Register (DMAMOD2)
376
DMA Software Request Register (DMASRR – Write Format)
377
Software Request Register (DMASRR)
377
DMA Software Request Register (DMASRR – Read Format)
378
Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK)
379
DMA Channel Mask Register (DMAMSK)
379
DMA Group Channel Mask Register (DMAGRPMSK)
380
Bus Size Register (DMABSR)
381
DMA Bus Size Register (DMABSR)
381
Chaining Register (DMACHR)
382
DMA Chaining Register (DMACHR)
382
DMA Interrupt Enable Register (DMAIEN)
383
Interrupt Enable Register (DMAIEN)
383
DMA Interrupt Status Register (DMAIS)
384
Interrupt Status Register (DMAIS)
384
Design Considerations
385
DMA Software Commands
385
Programming Considerations
385
Software Commands
385
DMA Controller Code Examples
386
Synchronous Serial I/O Unit
398
Overview
400
Ssio Operation
400
Transmitter and Receiver in Master Mode
401
Transmitter in Master Mode, Receiver in Slave Mode
401
Baud-Rate Generator
402
Transmitter and Receiver in Slave Mode
402
Transmitter in Slave Mode, Receiver in Master Mode
402
SSIO Signals
403
Clock Sources for the Baud-Rate Generator
404
Maximum and Minimum Baud-Rate Output Frequencies
405
Transmitter
405
SSIO Transmitter with Autotransmit Mode Enabled
406
Transmit Mode Using Enable Bit
406
SSIO Transmitter with Autotransmit Mode Disabled
407
Transmit Data by Polling
408
Interrupt Service Routine for Transmitting Data Using Interrupts
409
Autotransmit Mode
411
Receiver
411
Slave Mode
411
Receive Data by Polling
412
Interrupt Service Routine for Receiving Data Using Interrupts
413
Receiver Master Mode, Single Word Transfer
414
Register Definitions
415
SSIO Registers
415
Pin Configuration Register (PINCFG)
416
SIO and SSIO Configuration Register (SIOCFG)
417
Clock Prescale Register (CLKPRS)
418
Prescale Clock Register (CLKPRS)
418
SSIO Baud-Rate Control Register (SSIOBAUD)
419
SSIO Baud-Rate Count down Register (SSIOCTR)
420
SSIO Control 1 Register (SSIOCON1)
420
SSIO Control 1 Register (SSIOCON1)
421
SSIO Control 2 Register (SSIOCON2)
422
SSIO Transmit Holding Buffer (SSIOTBUF)
423
Design Considerations
424
SSIO Receive Holding Buffer (SSIORBUF)
424
Programming Considerations
425
SSIO Example Code
425
Chip-Select Unit
434
Overview
436
Csu Operation
437
Csu Upon Reset
437
Defining a Channel's Address Block
437
Channel Address Comparison Logic
438
Determining a Channel's Address Block Size
439
System Management Mode Support
445
Bus Cycle Length Control
446
Bus Size Control
446
Overlapping Regions
446
Bus Cycle Length Adjustments for Overlapping Regions
447
CSU Signals
448
Register Definitions
448
CSU Registers
449
Pin Configuration Register (PINCFG)
450
Port 2 Configuration Register (P2CFG)
451
Chip-Select Address Registers
452
Chip-Select High Address Register (CS N ADH, UCSADH)
452
Chip-Select Low Address Register (CS N ADL, UCSADL)
453
Chip-Select High Mask Registers (CS N MSKH, UCSMSKH)
454
Chip-Select Mask Registers
454
Chip-Select Low Mask Registers (CS N MSKL, UCSMSKL)
455
Design Considerations
456
Chip-Select Unit Code Example
457
Programming Considerations
457
Refresh Control Unit
460
Dynamic Memory Control
462
Refresh Methods
462
Refresh Control Unit Overview
463
Refresh Control Unit Connections
464
RCU Signals
465
Refresh Addresses
465
Refresh Intervals
465
Bus Arbitration
466
Rcu Operation
466
RCU Registers
467
Register Definitions
467
Refresh Clock Interval Register (RFSCIR)
468
Refresh Control Register (RFSCON)
469
Refresh Base Address Register (RFSBAD)
470
Refresh Address Register (RFSADD)
471
Connections to Ensure Refresh of All Rows in an 8-Bit Wide PSRAM Device
472
Design Considerations
472
RAS# Only Refresh Logic: Paged Mode
474
Programming Considerations
475
RAS# Only Refresh Logic: Non-Paged Mode
475
Refresh Control Unit Example Code
475
Input/Output Ports
478
Overview
480
I/O Port Block Diagram
481
Port Functionality
481
Logic Diagram of a Bi-Directional Port
482
Pin Multiplexing
484
I/O Port Registers
485
Register Definitions
485
Pin Configuration
486
Port N Configuration Register (P N CFG)
486
Port Data Latch Register (P N LTC)
487
Port Direction Register (P N DIR)
487
Port Pin State Register (P N PIN)
488
Design Considerations
489
Initialization Sequence
489
Pin Status During and after Reset
489
I/O Ports Code Example
490
Programming Considerations
490
Watchdog Timer Unit
494
Overview
496
Watchdog Timer Unit Connections
497
Watchdog Timer Unit Operation
498
WDT Signals
498
General-Purpose Timer Mode
499
Idle and Powerdown Modes
499
Bus Monitor Mode
500
Software Watchdog Mode
500
Disabling the Wdt
501
Register Definitions
502
WDT Registers
502
WDT Counter Value Registers (WDTCNTH and WDTCNTL)
503
WDT Status Register (WDTSTATUS)
504
WDT Reload Value Registers (WDTRLDH and WDTRLDL)
505
Power Control Register (PWRCON)
506
Design Considerations
507
Minimum Counter Reload Value
507
Programming Considerations
507
Watchdog Timer Unit Code Examples
507
Writing to the WDT Reload Registers (WDTRLDH and WDTRLDL)
507
Jtag Test-Logic Unit
512
Overview
514
Test Logic Unit Connections
515
Test Access Port (TAP)
516
Test Access Port Dedicated Pins
516
Test-Logic Unit Operation
516
Test Access Port (TAP) Controller
517
Example TAP Controller State Selections
518
TAP Controller (Finite-State Machine)
519
Instruction Register (IR)
520
Test-Logic Unit Instructions
520
Data Registers
521
Identification Code Register (IDCODE)
521
Boundary-Scan Register Bit Assignments
522
Bypassing Devices on a Board
523
Identifying the Device
523
Sampling Device Operation and Preloading Data
523
Testing
523
Testing the Interconnections (EXTEST)
523
Disabling the Output Drivers
524
Internal and External Timing for Loading the Instruction Register
525
Timing Information
525
Internal and External Timing for Loading a Data Register
526
Design Considerations
527
Appendix Asignal Descriptions
530
Compatibility with the Pc/At* Architecture
540
Hardware Departures from Pc/At System Architecture
542
DMA Unit
542
B.1.1 DMA Unit
542
Industry Standard Bus (ISA) Signals
543
B-1 Derivation of AEN Signal in a Typical PC/AT System
544
B-2 Derivation of AEN Signal for Intel386™ EX Processor-Based Systems
544
Interrupt Control Unit
545
SIO Units
545
B.1.4 SIO Units
545
CPU-Only Reset
545
HOLD, HLDA Pins
545
Port B
546
Software Considerations for a Pc/At System Architecture
546
Embedded Basic Input Output System (BIOS
546
Embedded Disk Operating System (DOS
546
Microsoft* Windows
546
B.1.7 Port B
546
B.2 Software Considerations for a Pc/At System Architecture
546
B.2.1 Embedded Basic Input Output System (BIOS)
546
B.2.2 Embedded Disk Operating System (DOS)
546
B.2.3 Microsoft* Windows*
546
Example Code Header Files
548
Register Definitions for Code Examples
550
C.2 Example Code Defines
555
System Register Quick Reference
564
Peripheral Register Addresses
566
Clkprs
572
D.2 Clkprs
572
CS N ADH (UCSADH
573
D.3 CS N ADH (UCSADH)
573
CS N ADL (UCSADL
574
D.4 CS N ADL (UCSADL)
574
CS N MSKH (UCSMSKH
575
D.5 CS N MSKH (UCSMSKH)
575
CS N MSKL (UCSMSKL
576
D.6 CS N MSKL (UCSMSKL)
576
DLL N and DLH N
577
Dmabsr
578
D.8 Dmabsr
578
Dmacfg
579
D.9 Dmacfg
579
Dmachr
580
D.10 Dmachr
580
Dmacmd1
581
D.11 Dmacmd1
581
Dmacmd2
582
D.12 Dmacmd2
582
Dmagrpmsk
583
D.13 Dmagrpmsk
583
Dmaien
584
D.14 Dmaien
584
Dmais
585
D.15 Dmais
585
Dmamod1
586
D.16 Dmamod1
586
Dmamod2
587
D.17 Dmamod2
587
Dmamsk
588
D.18 Dmamsk
588
DMA N BYC N, DMA N REQ N and DMA N TAR N
589
Dmaovfe
590
D.20 Dmaovfe
590
Dmasrr
591
D.21 Dmasrr
591
Dmasts
592
D.22 Dmasts
592
Icw1 (Master and Slave
593
Icw2 (Master and Slave
594
Icw3 (Master
594
D.25 Icw3 (Master)
594
Icw3 (Slave
595
D.26 Icw3 (Slave)
595
Icw4 (Master and Slave
595
Idcode
596
D.28 Idcode
596
IER N
597
IIR N
598
Intcfg
599
D.31 Intcfg
599
LCR N
601
LSR N
602
MCR N
603
MSR N
604
Ocw1 (Master and Slave
605
Ocw2 (Master and Slave
606
Ocw3 (Master and Slave
607
P1Cfg
608
D.40 P1Cfg
608
P2Cfg
609
D.41 P2Cfg
609
P3Cfg
610
D.42 P3Cfg
610
Pincfg
611
D.43 Pincfg
611
P N dir
612
P N LTC
613
P N PIN
613
Poll (Master and Slave
614
Port92
615
D.48 Port92
615
Pwrcon
616
D.49 Pwrcon
616
RBR N
617
Remapcfg
618
D.51 Remapcfg
618
Rfsadd
619
Rfsbad
619
D.52 Rfsadd
619
D.53 Rfsbad
619
Rfscir
620
Rfscon
620
D.54 Rfscir
620
D.55 Rfscon
620
SCR N
621
Siocfg
622
D.57 Siocfg
622
Ssiobaud
623
D.58 Ssiobaud
623
Ssiocon1
624
D.59 Ssiocon1
624
Ssiocon2
625
D.60 Ssiocon2
625
Ssioctr
626
Ssiorbuf
626
D.61 Ssioctr
626
D.62 Ssiorbuf
626
Ssiotbuf
627
TBR N
627
D.63 Ssiotbuf
627
Tmrcfg
628
D.65 Tmrcfg
628
Tmrcon
629
D.66 Tmrcon
629
TMR N
630
Ucsadh
632
Ucsadl
632
Ucsmskh
632
Ucsmskl
632
D.68 Ucsadh
632
D.69 Ucsadl
632
D.70 Ucsmskh
632
D.71 Ucsmskl
632
Wdtcnth and Wdtcntl
633
Wdtrldh and Wdtrldl
634
Wdtstatus
635
D.74 Wdtstatus
635
Instruction Set Summary
638
Instruction Encoding and Clock Count Summary
638
E-1 Instruction Set Summary
639
Instruction Set Summary
640
Instruction Encoding
659
E.2 Instruction Encoding
659
E-1 General Instruction Format
659
32-Bit Extensions of the Instruction Set
660
E-2 Fields Within Instructions
660
Encoding of Instruction Fields
661
Encoding of Operand Length (W) Field
661
Encoding of the General Register (Reg) Field
661
Encoding of the Segment Register (Sreg) Field
662
Encoding of Address Mode
663
E-7 Encoding of 16-Bit Address Mode with "Mod R/M" Byte
664
E-8 Encoding of 32-Bit Address Mode with "Mod R/M" Byte (no S-I-B Byte Present)
665
E-9 Encoding of 32-Bit Address Mode ("Mod R/M" Byte and S-I-B Byte Present)
666
Encoding of Operation Direction (D) Field
667
Encoding of Sign-Extend (S) Field
667
Encoding of Conditional Test (Tttn) Field
667
Encoding of Control or Debug or Test Register (Eee) Field
668
Glossary
670
Index
678
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Intel 386 Specifications
General
Brand
Intel
Model
386
Category
Computer Hardware
Language
English
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