Intel 386

10-17
TIMER/COUNTER UNIT
Figure 10-17 shows suspending the counting sequence. A low level on GATEn causes the counter
to suspend counting (both the state of OUTn and the count remain unchanged). A high level on
GATEn resumes counting.
Figure 10-17. Mode 4 – Disabling the Count
Figure 10-18 shows writing a new count. On the CLKINn pulse following the new count write,
the counter loads the new count and counting continues from the new count.
Figure 10-18. Mode 4 – Writing a New Count
A2402-01
????0003 0003 0003 0002 0001 0000 FFFF
Writes to
Counter
n
CLKIN n
GATE n
OUT n
Control
Word = 18H
Count
Count = 3
????0003 0002 0001 0002 0001 0000 FFFF
Writes to
Counter
n
CLKIN n
GATE n
OUT n
Control
Word = 18H
Count
Count = 2
Count = 3
A2403-01