Intel 386

9-5
INTERRUPT CONTROL UNIT
Table 9-1. 82C59A Master and Slave Interrupt Sources
Master IR
Line
Source
Connected
by
Slave
IR Line
Source
Connected
by
IR0 TMROUT0
(timer control unit)
Hardwired IR0 V
SS
INTCFG.0=0
INT4
(device pin)
INTCFG.0=1
IR1 V
SS
P3CFG.2=0 IR1 SSIOINT
(SSIO unit)
INTCFG.1=0
INT0
(device pin)
P3CFG.2=1 INT5
(Device pin)
INTCFG.1=1
IR2 Slave 82C59A
Cascade
Hardwired IR2 TMROUT1
(timer control unit)
Hardwired
IR3 SIOINT1
(SIO unit)
INTCFG.6=0
P3CFG.1=0
IR3 TMROUT2
(timer control unit)
Hardwired
INT8
(device pin)
INTCFG.6=1
P3CFG.1=1
MCR0.3=1
IR4 SIOINT0
(SIO unit)
INTCFG.5=0
P3CFG.0=0
IR4 DMAINT
(DMA unit)
INTCFG.4=0
INT9
(device pin)
INTCFG.5=1
P3CFG.0=1
MCR1.3=1
INT6
(device pin)
INTCFG.4=1
IR5 V
SS
P3CFG.3=0 IR5 INT6
(device pin)
INTCFG.4=0
INTCFG.2=1
INT1
(device pin)
P3CFG.3=1 DMAINT
(DMA unit)
INTCFG.4=1
INTCFG.2=1
IR6 V
SS
P3CFG.4=0 IR6 V
SS
INTCFG.3=0
INT2
(device pin)
P3CFG.4=1 INT7
(device pin)
INTCFG.3=1
IR7 V
SS
P3CFG.5=0 IR7 WDTOUT#
(watchdog timer)
Hardwired
INT3
(device pin)
P3CFG.5=1