Intel 386

12-43
DMA CONTROLLER
Read DMASRR to see whether a software request for a particular channel is pending. Each re-
quest bit is cleared upon Terminal Count or external EOP#. When in auto-initialize mode, both
bits are cleared when a Terminal Count or external EOP# occurs.
Figure 12-28. DMA Software Request Register (DMASRR – read format)
DMA Software Request (read format)
DMASRR
Expanded Addr:
ISA Addr:
Reset State:
F009H
0009H
00H
7 0
———— ——SR1SR0
Bit
Number
Bit
Mnemonic
Function
7–2 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
1 SR1 Software Request 1:
When set, this bit indicates that channel 1 has a software request
pending.
0 SR0 Software Request 0:
When set, this bit indicates that channel 0 has a software request
pending.