Name: Intel 386
Brand: Intel
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Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

D-24

D.19 DMA

BYC

DMA

REQ

AND

DMA

TAR

DMA Channel 0

DMA Channel 1

24 16 8 0

Requester Address DMA0REQ3 DMA0REQ2 DMA0REQ1 DMA0REQ0

F011H

(BP=1) F011H (BP=0) F010H (BP=1) F010H (BP=0)

24 16 8 0

Target Address DMA0TAR3 DMA0TAR2 DMA0TAR1 DMA0TAR0

F086H F087H F000H

(BP=1) F000H (BP=0)

16 8 0

Byte Count DMA0BYC2 DMA0BYC1 DMA0BYC0

F098H F001H

(BP=1) F001H (BP=0)

24 16 8 0

Requester Address DMA1REQ3 DMA1REQ2 DMA1REQ1 DMA1REQ0

F013H

(BP=1) F013H (BP=0) F012H (BP=1) F012H (BP=0)

24 16 8 0

Target Address DMA1TAR3 DMA1TAR2 DMA1TAR1 DMA1TAR0

F085H F083H F002H

(BP=1) F002H (BP=0)

16 8 0

Byte Count DMA1BYC2 DMA1BYC1 DMA1BYC0

F099H F003H

(BP=1) F003H (BP=0)

Table of Contents4
Guide to this Manual26
Manual Contents28
Notational Conventions30
Special Terminology31
Related Documents32
Electronic Support Systems33
Faxback Service33
Bulletin Board System (BBS)34
Compuserve Forums34
Technical Support34
World Wide Web34
Product Literature35
Architectural Overview36
Intel386 EX EMBEDDED PROCESSOR CORE38
Intel386™ EX Embedded Processor Block Diagram39
Integrated Peripherals40
PC-Compatible Peripherals40
Embedded Application-Specific Peripherals41
Core Overview42
Additional Address Lines44
Intel386 CX PROCESSOR ENHANCEMENTS44
System Management Mode44
Instruction Pipelining45
Intel386 CX PROCESSOR INTERNAL ARCHITECTURE45
The Intel386™ CX Processor Internal Block Diagram46
Core Bus Unit47
Instruction Decode Unit47
Instruction Prefetch Unit47
Execution Unit48
Paging Unit48
Segmentation Unit48
CORE Intel386 EX PROCESSOR INTERFACE49
System Register Organization50
Overview52
I/O Address Space for Pc/At Systems53
Intel386 EX Processor Peripheral Registers53
Intel386 Processor Core Architecture Registers53
Expanded I/O Address Space54
PC/AT I/O Address Space (10-Bit Decode)54
Expanded I/O Address Space (16-Bit Decode)55
Organization of Peripheral Registers56
Peripheral Register I/O Address Map in Slot 1556
Address Configuration Register57
I/O Address Decoding Techniques57
Address Configuration Register (REMAPCFG)58
Enabling and Disabling the Expanded I/O Space59
Programming REMAPCFG Example59
Setting the ESE Bit Code Example59
Addressing Modes60
DOS-Compatible Mode60
DOS-Compatible Mode61
Enhanced DOS Mode62
Non-DOS Mode62
Nonintrusive DOS Mode62
Example of Nonintrusive DOS-Compatible Mode63
Enhanced DOS Mode64
Nondos Mode65
Peripheral Register Addresses66
Device Configuration72
Introduction74
Peripheral and Pin Connections75
DMA Controller, Bus Arbiter, and Refresh Unit Configuration76
DMA Service to an SIO or SSIO Peripheral76
Peripheral Configuration76
Using the DMA Unit with External Devices76
Limitations Due to Pin Signal Multiplexing77
Using the Timer to Initiate DMA Transfers77
Configuration of DMA, Bus Arbiter, and Refresh Unit78
DMA Configuration Register (DMACFG)79
Interrupt Control Unit Configuration80
Master's IR3 Connections81
Master's IR4 Connections81
Interrupt Control Unit Configuration82
Interrupt Configuration Register (INTCFG)83
Timer/Counter Unit Configuration84
Timer/Counter Unit Configuration85
Timer Configuration Register (TMRCFG)86
Asynchronous Serial I/O Configuration87
Serial I/O Unit 0 Configuration88
Serial I/O Unit 1 Configuration89
SIO and SSIO Configuration Register (SIOCFG)90
SSIO Unit Configuration91
Synchronous Serial I/O Configuration91
Chip-Select Unit and Clock and Power Management Unit Configuration92
Configuration of Chip-Select Unit and Clock and Power Management Unit93
Core Configuration94
Port 92 Configuration Register (PORT92)95
Pin Configuration96
Signal Pairs on Pins Without a Multiplexer96
Pin Configuration Register (PINCFG)97
Port 1 Configuration Register (P1CFG)98
Port 2 Configuration Register (P2CFG)99
Port 3 Configuration Register (P3CFG)100
Configuration Example101
Device Configuration Procedure101
Example Design Requirements101
Example Design Solution102
Example Pin Configuration Registers103
Example DMACFG Configuration Register104
Example TMRCFG Configuration Register105
Example INTCFG Configuration Register106
Example SIOCFG Configuration Register106
Pin Configuration Register Design Woksheet107
DMACFG Register Design Worksheet108
TMRCFG Register Design Worksheet109
INTCFG Register Design Worksheet110
SIOCFG Register Design Worksheet110
Bus Interface Unit112
Overview114
Bus Interface Unit Signals116
Bus Signal Descriptions116
Bus Operation118
Bus Status Definitions118
Basic External Bus Cycles119
Bus States120
Pipelining121
Data Bus Transfers and Operand Alignment122
Ready Logic123
Sequence of Nonaligned Bus Transfers123
Ready Logic124
Basic Internal and External Bus Cycles125
Bus Cycles126
Read Cycle126
Nonpipelined Address Read Cycles128
Write Cycle129
Nonpipelined Address Write Cycles131
Pipelined Cycle132
Complete Bus States (Including Pipelined Address)133
Pipelined Address Cycles134
Interrupt Acknowledge Cycle136
Interrupt Acknowledge Cycles138
Halt/Shutdown Cycle139
Halt Cycle140
Refresh Cycle141
Basic Refresh Cycle142
Refresh Cycle During HOLD/HLDA143
BS8 Cycle144
Read Cycles144
Write Cycles144
Bit Cycles to 8-Bit Devices (Using BS8#)146
Bus Lock147
Locked Cycle Activators147
Locked Cycle Timing147
External Bus Master Support (Using Hold, Hlda)148
LOCK# Signal Duration148
LOCK# Signal During Address Pipelining148
HOLD/HLDA Timing149
HOLD Signal Latency150
Design Considerations151
Interface to Intel387™ SX Math Coprocessor151
Intel386 EX Processor to Intel387 SX Math Coprocessor Interface152
System Configuration152
Software Considerations153
Intel386 EX Processor to SRAM/FLASH Interface154
SRAM/FLASH Interface154
Intel386 EX Processor to PSRAM Interface155
PSRAM Interface155
Intel386 EX Processor to Paged DRAM Interface156
Paged DRAM Interface156
Intel386 EX Processor and Non-Paged DRAM Interface157
Non-Paged DRAM Interface157
System Management Mode158
Smm Hardware Interface160
System Management Interrupt Input (SMI#)160
System Management Mode Overview160
SMM Active Output (SMIACT#)161
System Management RAM (SMRAM)161
CR0 Bits Cleared Upon Entering SMM162
Register Status During SMM162
System Management Mode Programming and Configuration162
SMM Processor State Initialization Values163
System Management Interrupt163
Standard SMI#164
SMIACT# Latency165
Relative Priority of Exceptions and Interrupts166
SMI# Priority166
SMI# During HALT167
System Management Interrupt During HALT Cycle167
HALT Restart168
SMI# During I/O Instruction168
System Management Interrupt During I/O Instruction168
I/O Restart169
Interrupt During SMM Handler169
SMI# Timing169
SMM Handler Interruption169
HALT During SMM Handler170
Interrupted SMI# Service170
Chip-Select Unit Support for SMRAM171
HALT During SMM Handler171
Idle Mode and Powerdown Mode During SMM171
SMI# During SMM Operation171
SMRAM Programming171
SMRAM State Dump Area173
Resume Instruction (RSM)174
THE Intel386 EX PROCESSOR IDENTIFIER REGISTERS174
Programming Considerations175
System Management Mode Code Example175
Clock and Power Management Unit180
Clock Generation Logic182
Overview182
Clock and Power Management Unit Connections183
Clock Synchronization184
Power Management Logic184
SMM Interaction with Power Management Modes185
Bus Interface Unit Operation During Idle Mode186
SMM Interaction with Idle and Powerdown Modes186
Watchdog Timer Unit Operation During Idle Mode186
Clock and Power Management Registers and Signals187
Clock and Power Management Signals187
Clock Prescale Register (CLKPRS)188
Controlling the Psclk Frequency188
Controlling Power Management Modes189
Power Control Register (PWRCON)189
Idle Mode190
Timing Diagram, Entering and Leaving Idle Mode190
Powerdown Mode191
Ready Generation During HALT191
Design Considerations192
Reset Considerations192
Timing Diagram, Entering and Leaving Powerdown Mode192
Built-In Self Test193
JTAG Reset193
Power-Up Considerations193
Reset Synchronization Circuit193
Clock and Power Management Unit Code Example194
Powerdown Mode and Idle Mode Considerations194
Programming Considerations194
Interrupt Control Unit198
Overview200
Interrupt Control Unit Configuration202
Icu Operation203
Interrupt Sources203
C59A Master and Slave Interrupt Sources204
Assigning an Interrupt Level205
Interrupt Priority205
Determining Priority206
Methods for Changing the Default Interrupt Structure206
Interrupt Vectors207
Interrupt Process208
Interrupt Process – Master Request from Non-Slave Source210
Interrupt Process – Slave Request211
Interrupt Process – Master Request from Slave Source212
Poll Mode213
Register Definitions214
ICU Registers215
Port 3 Configuration Register (P3CFG)217
Interrupt Configuration Register (INTCFG)218
Initialization Command Word 1 (ICW1)219
Initialization Command Word 1 Register (ICW1)219
Initialization Command Word 2 (ICW2)220
Initialization Command Word 2 Register (ICW2)220
Initialization Command Word 3 (ICW3)221
Initialization Command Word 3 Register (ICW3 – Master)221
Initialization Command Word 3 Register (ICW3 – Slave)222
Initialization Command Word 4 (ICW4)223
Initialization Command Word 4 Register (ICW4)223
Operation Command Word 1 (OCW1)224
Operation Command Word 2 (OCW2)225
Operation Command Word 3 (OCW3)226
In-Service Register (ISR)227
Interrupt Request Register (IRR)227
Poll Status Byte (POLL)227
Design Considerations228
Interrupt Acknowledge Cycle228
Interrupt Detection228
Cascading Interrupt Controllers229
Spurious Interrupts229
Cascading External 82C59A Interrupt Controllers230
Interrupt Control Unit Code Examples231
Programming Considerations231
Timer/Counter Unit242
Overview244
Timer/Counter Unit Signal Connections245
TCU Signals and Registers246
TCU Associated Registers247
Tcu Operation248
Mode 0 - Interrupt on Terminal Count249
Operations Caused by GATE N249
Mode 0 – Basic Operation250
Mode 0 – Disabling the Count250
Mode 0 – Writing a New Count251
Mode 1 - Hardware Retriggerable One-Shot251
Mode 1 – Basic Operation252
Mode 1 – Retriggering the One-Shot252
Mode 1 – Writing a New Count253
Mode 2 - Rate Generator253
Mode 2 – Basic Operation254
Mode 2 – Disabling the Count254
Mode 2 – Writing a New Count255
Mode 3 - Square Wave255
Mode 3 – Basic Operation (Even Count)256
Mode 3 – Basic Operation (Odd Count)257
Mode 3 – Disabling the Count257
Mode 3 – Writing a New Count (Without a Trigger)258
Mode 4 - Software-Triggered Strobe259
Mode 4 – Basic Operation259
Mode 4 – Disabling the Count260
Mode 4 – Writing a New Count260
Mode 5 - Hardware-Triggered Strobe261
Mode 5 – Basic Operation261
Mode 5 – Retriggering the Strobe262
Mode 5 – Writing a New Count Value262
Configuring the Input and Output Signals263
GATE N Connection Options263
Hardware Control of GATE N263
Register Definitions263
Software Control of GATE N263
Timer Configuration Register (TMRCFG)264
Port 3 Configuration Register (P3CFG)265
Pin Configuration Register (PINCFG)266
Initializing the Counters267
Timer Control Register (TMRCON – Control Word Format)268
Minimum and Maximum Initial Counts269
Timer N Register (TMR N – Write Format)269
Writing the Counters269
Counter-Latch Command270
Reading the Counter270
Simple Read270
Timer Control Register (TMRCON – Counter-Latch Format)271
Timer N Register (TMR N – Read Format)272
Read-Back Command273
Timer Control Register (TMRCON – Read-Back Format)273
Timer N Register (TMR N – Status Format)275
Programming Considerations276
Results of Multiple Read-Back Commands Without Reads276
Timer/Counter Unit Code Examples277
Asynchronous Serial I/O Unit286
Overview288
Serial I/O Unit 1 Configuration289
SIO Signals290
Baud-Rate Generator291
SIO N Baud-Rate Generator Clock Sources291
Sio Operation291
Divisor Values for Common Bit Rates292
Maximum and Minimum Output Bit Rates292
SIO N Transmitter293
SIO N Transmitter294
SIO N Data Transmission Process Flow295
SIO N Receiver296
SIO N Data Reception Process Flow298
Diagnostic Mode299
Modem Control299
SIO DMA Sources300
SIO Interrupt and DMA Sources300
SIO Interrupt Sources300
Status Signal Priorities and Sources300
External UART Support301
Register Definitions302
SIO Registers302
Access to Multiplexed Registers303
Pin and Port Configuration Registers (PINCFG and P N CFG [ N = 1-3])304
Pin Configuration Register (PINCFG)304
Port 1 Configuration Register (P1CFG)305
Port 2 Configuration Register (P2CFG)306
Port 3 Configuration Register (P3CFG)307
SIO and SSIO Configuration Register (SIOCFG)308
Divisor Latch Registers (DLL N and DLH N )309
Transmit Buffer Register (TBR N )310
Receive Buffer Register (RBR N )311
Serial Line Control Register (LCR N )312
Serial Line Status Register (LSR N )313
Interrupt Enable Register (IER N )314
Interrupt ID Register (IIR N )315
Modem Control Register (MCR N )316
Modem Control Signals – Diagnostic Mode Connections316
Modem Control Signals – Internal Connections316
Modem Control Register (MCR N )317
Modem Status Register (MSR N )318
Programming Considerations319
Scratch Pad Register (SCR N )319
Asynchronous Serial I/O Unit Code Examples320
Dma Controller334
Overview336
DMA Unit Block Diagram337
DMA Terminology338
DMA Signals339
Bus Cycle Options for Data Transfers340
Dma Operation340
DMA Transfers340
Fly-By Mode340
Operations Performed During Transfer341
Programmable DMA Transfer Direction341
Two-Cycle Mode341
DMA Usage of the 4-Byte Temporary Register342
Ready Generation for DMA Cycles342
DMA Temporary Buffer Operation for a Read Transfer343
DMA Temporary Buffer Operation for a Write Transfer343
Bus Control Arbitration344
Start of a Two-Cycle DMA Transfer Initiated by DRQ N344
Starting DMA Transfers344
Changing the Priority of the DMA Channel and External Bus Requests345
Ending DMA Transfers345
Buffer Transfer Ended by an Expired Byte Count346
Buffer Transfer Ended by the EOP# Input346
Autoinitialize Buffer-Transfer Mode347
Buffer-Transfer Modes347
Chaining Buffer-Transfer Mode347
Single Buffer-Transfer Mode347
Data-Transfer Modes348
Single Data-Transfer Mode349
Single Data-Transfer Mode with Single Buffer-Transfer Mode350
Single Data-Transfer Mode with Autoinitialize Buffer-Transfer Mode351
Single Data-Transfer Mode with Chaining Buffer-Transfer Mode352
Block Data-Transfer Mode353
Block Data-Transfer Mode with Single Buffer-Transfer Mode354
Block Data-Transfer Mode with Autoinitialize Buffer-Transfer Mode355
Buffer Transfer Suspended by the Deactivation of DRQ N356
Demand Data-Transfer Mode356
Demand Data-Transfer Mode with Single Buffer-Transfer Mode357
Demand Data-Transfer Mode with Autoinitialize Buffer-Transfer Mode358
Demand Data-Transfer Mode with Chaining Buffer-Transfer Mode359
Cascade Mode360
Cascade Mode361
DMA Interrupts361
8237A Compatibility362
DMA Registers363
Register Definitions363
Pin Configuration Register (PINCFG)366
DMA Configuration Register (DMACFG)367
Channel Registers368
DMA Overflow Enable Register (DMAOVFE)369
Overflow Enable Register (DMAOVFE)369
Command 1 Register (DMACMD1)370
DMA Command 1 Register (DMACMD1)370
DMA Status Register (DMASTS)371
Status Register (DMASTS)371
Command 2 Register (DMACMD2)372
DMA Command 2 Register (DMACMD2)372
Mode 1 Register (DMAMOD1)373
DMA Mode 1 Register (DMAMOD1)374
Mode 2 Register (DMAMOD2)375
DMA Mode 2 Register (DMAMOD2)376
DMA Software Request Register (DMASRR – Write Format)377
Software Request Register (DMASRR)377
DMA Software Request Register (DMASRR – Read Format)378
Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK)379
DMA Channel Mask Register (DMAMSK)379
DMA Group Channel Mask Register (DMAGRPMSK)380
Bus Size Register (DMABSR)381
DMA Bus Size Register (DMABSR)381
Chaining Register (DMACHR)382
DMA Chaining Register (DMACHR)382
DMA Interrupt Enable Register (DMAIEN)383
Interrupt Enable Register (DMAIEN)383
DMA Interrupt Status Register (DMAIS)384
Interrupt Status Register (DMAIS)384
Design Considerations385
DMA Software Commands385
Programming Considerations385
Software Commands385
DMA Controller Code Examples386
Synchronous Serial I/O Unit398
Overview400
Ssio Operation400
Transmitter and Receiver in Master Mode401
Transmitter in Master Mode, Receiver in Slave Mode401
Baud-Rate Generator402
Transmitter and Receiver in Slave Mode402
Transmitter in Slave Mode, Receiver in Master Mode402
SSIO Signals403
Clock Sources for the Baud-Rate Generator404
Maximum and Minimum Baud-Rate Output Frequencies405
Transmitter405
SSIO Transmitter with Autotransmit Mode Enabled406
Transmit Mode Using Enable Bit406
SSIO Transmitter with Autotransmit Mode Disabled407
Transmit Data by Polling408
Interrupt Service Routine for Transmitting Data Using Interrupts409
Autotransmit Mode411
Receiver411
Slave Mode411
Receive Data by Polling412
Interrupt Service Routine for Receiving Data Using Interrupts413
Receiver Master Mode, Single Word Transfer414
Register Definitions415
SSIO Registers415
Pin Configuration Register (PINCFG)416
SIO and SSIO Configuration Register (SIOCFG)417
Clock Prescale Register (CLKPRS)418
Prescale Clock Register (CLKPRS)418
SSIO Baud-Rate Control Register (SSIOBAUD)419
SSIO Baud-Rate Count down Register (SSIOCTR)420
SSIO Control 1 Register (SSIOCON1)420
SSIO Control 1 Register (SSIOCON1)421
SSIO Control 2 Register (SSIOCON2)422
SSIO Transmit Holding Buffer (SSIOTBUF)423
Design Considerations424
SSIO Receive Holding Buffer (SSIORBUF)424
Programming Considerations425
SSIO Example Code425
Chip-Select Unit434
Overview436
Csu Operation437
Csu Upon Reset437
Defining a Channel's Address Block437
Channel Address Comparison Logic438
Determining a Channel's Address Block Size439
System Management Mode Support445
Bus Cycle Length Control446
Bus Size Control446
Overlapping Regions446
Bus Cycle Length Adjustments for Overlapping Regions447
CSU Signals448
Register Definitions448
CSU Registers449
Pin Configuration Register (PINCFG)450
Port 2 Configuration Register (P2CFG)451
Chip-Select Address Registers452
Chip-Select High Address Register (CS N ADH, UCSADH)452
Chip-Select Low Address Register (CS N ADL, UCSADL)453
Chip-Select High Mask Registers (CS N MSKH, UCSMSKH)454
Chip-Select Mask Registers454
Chip-Select Low Mask Registers (CS N MSKL, UCSMSKL)455
Design Considerations456
Chip-Select Unit Code Example457
Programming Considerations457
Refresh Control Unit460
Dynamic Memory Control462
Refresh Methods462
Refresh Control Unit Overview463
Refresh Control Unit Connections464
RCU Signals465
Refresh Addresses465
Refresh Intervals465
Bus Arbitration466
Rcu Operation466
RCU Registers467
Register Definitions467
Refresh Clock Interval Register (RFSCIR)468
Refresh Control Register (RFSCON)469
Refresh Base Address Register (RFSBAD)470
Refresh Address Register (RFSADD)471
Connections to Ensure Refresh of All Rows in an 8-Bit Wide PSRAM Device472
Design Considerations472
RAS# Only Refresh Logic: Paged Mode474
Programming Considerations475
RAS# Only Refresh Logic: Non-Paged Mode475
Refresh Control Unit Example Code475
Input/Output Ports478
Overview480
I/O Port Block Diagram481
Port Functionality481
Logic Diagram of a Bi-Directional Port482
Pin Multiplexing484
I/O Port Registers485
Register Definitions485
Pin Configuration486
Port N Configuration Register (P N CFG)486
Port Data Latch Register (P N LTC)487
Port Direction Register (P N DIR)487
Port Pin State Register (P N PIN)488
Design Considerations489
Initialization Sequence489
Pin Status During and after Reset489
I/O Ports Code Example490
Programming Considerations490
Watchdog Timer Unit494
Overview496
Watchdog Timer Unit Connections497
Watchdog Timer Unit Operation498
WDT Signals498
General-Purpose Timer Mode499
Idle and Powerdown Modes499
Bus Monitor Mode500
Software Watchdog Mode500
Disabling the Wdt501
Register Definitions502
WDT Registers502
WDT Counter Value Registers (WDTCNTH and WDTCNTL)503
WDT Status Register (WDTSTATUS)504
WDT Reload Value Registers (WDTRLDH and WDTRLDL)505
Power Control Register (PWRCON)506
Design Considerations507
Minimum Counter Reload Value507
Programming Considerations507
Watchdog Timer Unit Code Examples507
Writing to the WDT Reload Registers (WDTRLDH and WDTRLDL)507
Jtag Test-Logic Unit512
Overview514
Test Logic Unit Connections515
Test Access Port (TAP)516
Test Access Port Dedicated Pins516
Test-Logic Unit Operation516
Test Access Port (TAP) Controller517
Example TAP Controller State Selections518
TAP Controller (Finite-State Machine)519
Instruction Register (IR)520
Test-Logic Unit Instructions520
Data Registers521
Identification Code Register (IDCODE)521
Boundary-Scan Register Bit Assignments522
Bypassing Devices on a Board523
Identifying the Device523
Sampling Device Operation and Preloading Data523
Testing523
Testing the Interconnections (EXTEST)523
Disabling the Output Drivers524
Internal and External Timing for Loading the Instruction Register525
Timing Information525
Internal and External Timing for Loading a Data Register526
Design Considerations527
Appendix Asignal Descriptions530
- Compatibility with the Pc/At* Architecture540
- Hardware Departures from Pc/At System Architecture542
- DMA Unit542
- B.1.1 DMA Unit542
- Industry Standard Bus (ISA) Signals543
- B-1 Derivation of AEN Signal in a Typical PC/AT System544
- B-2 Derivation of AEN Signal for Intel386™ EX Processor-Based Systems544
- Interrupt Control Unit545
- SIO Units545
- B.1.4 SIO Units545
- CPU-Only Reset545
- HOLD, HLDA Pins545
- Port B546
- Software Considerations for a Pc/At System Architecture546
- Embedded Basic Input Output System (BIOS546
- Embedded Disk Operating System (DOS546
- Microsoft* Windows546
- B.1.7 Port B546
- B.2 Software Considerations for a Pc/At System Architecture546
- B.2.1 Embedded Basic Input Output System (BIOS)546
- B.2.2 Embedded Disk Operating System (DOS)546
- B.2.3 Microsoft* Windows*546
- Example Code Header Files548
- Register Definitions for Code Examples550
- C.2 Example Code Defines555
- System Register Quick Reference564
- Peripheral Register Addresses566
- Clkprs572
- D.2 Clkprs572
- CS N ADH (UCSADH573
- D.3 CS N ADH (UCSADH)573
- CS N ADL (UCSADL574
- D.4 CS N ADL (UCSADL)574
- CS N MSKH (UCSMSKH575
- D.5 CS N MSKH (UCSMSKH)575
- CS N MSKL (UCSMSKL576
- D.6 CS N MSKL (UCSMSKL)576
- DLL N and DLH N577
- Dmabsr578
- D.8 Dmabsr578
- Dmacfg579
- D.9 Dmacfg579
- Dmachr580
- D.10 Dmachr580
- Dmacmd1581
- D.11 Dmacmd1581
- Dmacmd2582
- D.12 Dmacmd2582
- Dmagrpmsk583
- D.13 Dmagrpmsk583
- Dmaien584
- D.14 Dmaien584
- Dmais585
- D.15 Dmais585
- Dmamod1586
- D.16 Dmamod1586
- Dmamod2587
- D.17 Dmamod2587
- Dmamsk588
- D.18 Dmamsk588
- DMA N BYC N, DMA N REQ N and DMA N TAR N589
- Dmaovfe590
- D.20 Dmaovfe590
- Dmasrr591
- D.21 Dmasrr591
- Dmasts592
- D.22 Dmasts592
- Icw1 (Master and Slave593
- Icw2 (Master and Slave594
- Icw3 (Master594
- D.25 Icw3 (Master)594
- Icw3 (Slave595
- D.26 Icw3 (Slave)595
- Icw4 (Master and Slave595
- Idcode596
- D.28 Idcode596
- IER N597
- IIR N598
- Intcfg599
- D.31 Intcfg599
- LCR N601
- LSR N602
- MCR N603
- MSR N604
- Ocw1 (Master and Slave605
- Ocw2 (Master and Slave606
- Ocw3 (Master and Slave607
- P1Cfg608
- D.40 P1Cfg608
- P2Cfg609
- D.41 P2Cfg609
- P3Cfg610
- D.42 P3Cfg610
- Pincfg611
- D.43 Pincfg611
- P N dir612
- P N LTC613
- P N PIN613
- Poll (Master and Slave614
- Port92615
- D.48 Port92615
- Pwrcon616
- D.49 Pwrcon616
- RBR N617
- Remapcfg618
- D.51 Remapcfg618
- Rfsadd619
- Rfsbad619
- D.52 Rfsadd619
- D.53 Rfsbad619
- Rfscir620
- Rfscon620
- D.54 Rfscir620
- D.55 Rfscon620
- SCR N621
- Siocfg622
- D.57 Siocfg622
- Ssiobaud623
- D.58 Ssiobaud623
- Ssiocon1624
- D.59 Ssiocon1624
- Ssiocon2625
- D.60 Ssiocon2625
- Ssioctr626
- Ssiorbuf626
- D.61 Ssioctr626
- D.62 Ssiorbuf626
- Ssiotbuf627
- TBR N627
- D.63 Ssiotbuf627
- Tmrcfg628
- D.65 Tmrcfg628
- Tmrcon629
- D.66 Tmrcon629
- TMR N630
- Ucsadh632
- Ucsadl632
- Ucsmskh632
- Ucsmskl632
- D.68 Ucsadh632
- D.69 Ucsadl632
- D.70 Ucsmskh632
- D.71 Ucsmskl632
- Wdtcnth and Wdtcntl633
- Wdtrldh and Wdtrldl634
- Wdtstatus635
- D.74 Wdtstatus635
- Instruction Set Summary638
- Instruction Encoding and Clock Count Summary638
- E-1 Instruction Set Summary639
- Instruction Set Summary640
- Instruction Encoding659
- E.2 Instruction Encoding659
- E-1 General Instruction Format659
- 32-Bit Extensions of the Instruction Set660
- E-2 Fields Within Instructions660
- Encoding of Instruction Fields661
- Encoding of Operand Length (W) Field661
- Encoding of the General Register (Reg) Field661
- Encoding of the Segment Register (Sreg) Field662
- Encoding of Address Mode663
- E-7 Encoding of 16-Bit Address Mode with "Mod R/M" Byte664
- E-8 Encoding of 32-Bit Address Mode with "Mod R/M" Byte (no S-I-B Byte Present)665
- E-9 Encoding of 32-Bit Address Mode ("Mod R/M" Byte and S-I-B Byte Present)666
- Encoding of Operation Direction (D) Field667
- Encoding of Sign-Extend (S) Field667
- Encoding of Conditional Test (Tttn) Field667
- Encoding of Control or Debug or Test Register (Eee) Field668
- Glossary670
- Index678

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm

Intel 386 User Manual

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Intel 386 Specifications

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