Intel 386 User Manual

17-11
WATCHDOG TIMER UNIT
Figure 17-5. Power Control Register (PWRCON)
Power Control Register
PWRCON
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F800H
—
00H
7 0
— — — — WDTRDY HSREADY PC1 PC0
Bit
Number
Bit
Mnemonic
Function
7–4 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
3 WDTRDY Watch Dog Timer Ready:
0 = An external READY must be generated to terminate the cycle when
the WDT times out in Bus Monitor Mode.
1 = Internal logic generates READY# to terminate the cycle when the
WDT times out in Bus Monitor Mode.
2 HSREADY Halt/Shutdown Ready:
0 = An external ready must be generated to terminate a HALT/Shutdown
cycle.
1 = Internal logic generates READY# to terminate a HALT/Shutdown
cycle.
1–0 PC1:0 Power Control:
Program these bits, then execute a HALT instruction. The device enters
the programmed mode when READY# (internal or external) terminates
the halt bus cycle. When these bits have equal values, the HALT
instruction causes a normal halt and the device remains in active mode.
PC1 PC0
0 0 active mode
1 0 idle mode
01powerdown mode
1 1 active mode

Intel 386 Specifications

General

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm