Intel 386 User Manual

10-29
TIMER/COUNTER UNIT
You can interleave reads and writes of the same counter; for example, if the counter is pro-
grammed for the two-byte read/write selection, the following sequence is valid.
1. Read least-significant byte.
2. Write new least-significant byte.
3. Read most-significant byte.
4. Write new most-significant byte.
Figure 10-28. Timer n Register (TMR n – Read Format)
Timer n (Read Format)
TMR
n ( n = 0–2)
Expanded Addr:
ISA Addr:
Reset State:
F040H, F041H
F042H
0040H, 0041H
0042H
XXH
7 0
CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0
Bit
Number
Bit
Mnemonic
Function
7–0 CV7:0 Count Value:
These bits contain the counter’s count value. When reading the
counter’s count value, follow the read selection specified in the counter’s
control word.

Intel 386 Specifications

General

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm