Intel 386

16-3
INPUT/OUTPUT PORTS
Figure 16-2. Logic Diagram of a Bi-directional Port
0
1
S
Q
D
Q#
CK
P
n LTC
From Internal
Peripheral
Read Port
Data latch
Write Port
Data Latch
Read Port
Pin State
To Internal
Peripheral
Write Port
Direction
Read Port
Direction
Write Port
Control
Read Port
Control
Internal Data
Bus (F-Bus)
SYNC
Pin
A3266-01
Q
D
Q#
CK
P
n DIR
P
n PIN
V
CC

or
V
SS†
0
1
S
0
1
S
Q
D
Q#
CK
P
n CFG
From Internal
Peripheral
Direction
Control
† Depends on peripheral's inactive state