Intel 386 User Manual

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
15-8
15.4.2 Refresh Control Register (RFSCON)
Use RFSCON to enable and disable the refresh control unit and to check the current interval
counter value.
Figure 15-3. Refresh Control Register (RFSCON)
Refresh Control
RFSCON
(read/write)
Expanded Addr:
ISA Addr:
Reset State:
F4A4H
—
0000H
15 8
REN — — — — — CV9 CV8
7 0
CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0
Bit
Number
Bit
Mnemonic
Function
15 REN Refresh Control Unit Enable:
This bit enables or disables the refresh control unit.
0 = Disables refresh control unit
1 = Enables refresh control unit
14–10 — Reserved. These bits are undefined; for compatibility with future devices,
do not modify these bits.
9–0 CV9:0 Counter Value:
These read-only bits represent the current value of the interval counter.
Write operations to these bits have no effect.

Intel 386 Specifications

General

Architecture	x86
Clock Speed	12 MHz to 40 MHz
Transistor Count	275, 000
Data Bus Width	32-bit
Address Bus Width	32-bit
Instruction Set	x86
Introduced	1985
Maximum Memory	4 GB
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
MMU	Yes
Voltage	5V
Model	Intel 386
Package	PGA
Process	1.5 μm to 1 μm