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CONTENTS
15.2.3 Refresh Addresses .................................................................................................15-4
15.2.4 Bus Arbitration ........................................................................................................15-5
15.3 RCU OPERATION....................................................................................................... 15-5
15.4 REGISTER DEFINITIONS........................................................................................... 15-6
15.4.1 Refresh Clock Interval Register (RFSCIR) ..............................................................15-7
15.4.2 Refresh Control Register (RFSCON) ......................................................................15-8
15.4.3 Refresh Base Address Register (RFSBAD) ............................................................15-9
15.4.4 Refresh Address Register (RFSADD) ...................................................................15-10
15.5 DESIGN CONSIDERATIONS.................................................................................... 15-11
15.6 PROGRAMMING CONSIDERATIONS...................................................................... 15-14
15.6.1 Refresh Control Unit Example Code .....................................................................15-14
CHAPTER 16
INPUT/OUTPUT PORTS
16.1 OVERVIEW ................................................................................................................. 16-1
16.1.1 Port Functionality ....................................................................................................16-2
16.2 REGISTER DEFINITIONS........................................................................................... 16-6
16.2.1 Pin Configuration ....................................................................................................16-7
16.2.2 Initialization Sequence ..........................................................................................16-10
16.3 DESIGN CONSIDERATIONS.................................................................................... 16-10
16.3.1 Pin Status During and After Reset ........................................................................16-10
16.4 PROGRAMMING CONSIDERATIONS...................................................................... 16-11
16.4.1 I/O Ports Code Example .......................................................................................16-11
CHAPTER 17
WATCHDOG TIMER UNIT
17.1 OVERVIEW ................................................................................................................. 17-1
17.1.1 WDT Signals ...........................................................................................................17-3
17.2 WATCHDOG TIMER UNIT OPERATION.................................................................... 17-3
17.2.1 Idle and Powerdown modes ....................................................................................17-4
17.2.2 General-purpose Timer Mode .................................................................................17-4
17.2.3 Software Watchdog Mode .......................................................................................17-5
17.2.4 Bus Monitor Mode ...................................................................................................17-5
17.3 DISABLING THE WDT ................................................................................................ 17-6
17.4 REGISTER DEFINITIONS........................................................................................... 17-7
17.5 DESIGN CONSIDERATIONS.................................................................................... 17-12
17.6 PROGRAMMING CONSIDERATIONS...................................................................... 17-12
17.6.1 Writing to the WDT Reload Registers (WDTRLDH and WDTRLDL) ....................17-12
17.6.2 Minimum Counter Reload Value ...........................................................................17-12
17.6.3 Watchdog Timer Unit Code Examples ..................................................................17-12
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