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CONTENTS
APPENDIX E
INSTRUCTION SET SUMMARY
E.1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY.................................. E-1
E.2 INSTRUCTION ENCODING....................................................................................... E-22
E.2.1 32-bit Extensions of the Instruction Set ................................................................ E-23
E.2.2 Encoding of Instruction Fields ............................................................................... E-24
E.2.2.1 Encoding of Operand Length (w) Field ......................................................... E-24
E.2.2.2 Encoding of the General Register (reg) Field ............................................... E-24
E.2.2.3 Encoding of the Segment Register (sreg) Field ............................................ E-25
E.2.2.4 Encoding of Address Mode .......................................................................... E-26
E.2.2.5 Encoding of Operation Direction (d) Field .................................................... E-30
E.2.2.6 Encoding of Sign-Extend (s) Field ................................................................ E-30
E.2.2.7 Encoding of Conditional Test (tttn) Field ...................................................... E-30
E.2.2.8 Encoding of Control or Debug or Test Register (eee) Field ......................... E-31
GLOSSARY
INDEX
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