Intel 386

xvii
CONTENTS
FIGURES
Figure Page
6-16 Intel386 EX Processor to SRAM/FLASH Interface.....................................................6-41
6-17 Intel386 EX Processor to PSRAM Interface...............................................................6-42
6-18 Intel386 EX Processor to Paged DRAM Interface......................................................6-43
6-19 Intel386 EX Processor and Non-Paged DRAM Interface...........................................6-44
7-1 Standard SMI# .............................................................................................................7-5
7-2 SMIACT# Latency .......................................................................................................7-6
7-3 SMI# During HALT ......................................................................................................7-8
7-4 SMI# During I/O Instruction..........................................................................................7-9
7-5 SMI# Timing ...............................................................................................................7-10
7-6 Interrupted SMI# Service............................................................................................7-11
7-7 HALT During SMM Handler........................................................................................7-12
8-1 Clock and Power Management Unit Connections........................................................8-2
8-2 Clock Synchronization..................................................................................................8-3
8-3 SMM Interaction with Idle and Powerdown Modes.......................................................8-5
8-4 Clock Prescale Register (CLKPRS) .............................................................................8-7
8-5 Power Control Register (PWRCON).............................................................................8-8
8-6 Timing Diagram, Entering and Leaving Idle Mode .......................................................8-9
8-7 Timing Diagram, Entering and Leaving Powerdown Mode ........................................8-11
8-8 Reset Synchronization Circuit ....................................................................................8-12
9-1 Interrupt Control Unit Configuration..............................................................................9-3
9-2 Methods for Changing the Default Interrupt Structure..................................................9-7
9-3 Interrupt Process – Master Request from Non-slave Source.....................................9-11
9-4 Interrupt Process – Slave Request.............................................................................9-12
9-5 Interrupt Process – Master Request from Slave Source ............................................9-13
9-6 Port 3 Configuration Register (P3CFG)......................................................................9-18
9-7 Interrupt Configuration Register (INTCFG).................................................................9-19
9-8 Initialization Command Word 1 Register (ICW1)........................................................9-20
9-9 Initialization Command Word 2 Register (ICW2)........................................................9-21
9-10 Initialization Command Word 3 Register (ICW3 – Master).........................................9-22
9-11 Initialization Command Word 3 Register (ICW3 – Slave)...........................................9-23
9-12 Initialization Command Word 4 Register (ICW4)........................................................9-24
9-13 Operation Command Word 1 (OCW1) .......................................................................9-25
9-14 Operation Command Word 2 (OCW2) .......................................................................9-26
9-15 Operation Command Word 3 (OCW3) .......................................................................9-27
9-16 Poll Status Byte (POLL) .............................................................................................9-28
9-17 Interrupt Acknowledge Cycle......................................................................................9-29
9-18 Spurious Interrupts.....................................................................................................9-30
9-19 Cascading External 82C59A Interrupt Controllers......................................................9-31
10-1 Timer/Counter Unit Signal Connections.....................................................................10-2
10-2 Mode 0 – Basic Operation..........................................................................................10-7
10-3 Mode 0 – Disabling the Count....................................................................................10-7
10-4 Mode 0 – Writing a New Count...................................................................................10-8
10-5 Mode 1 – Basic Operation..........................................................................................10-9
10-6 Mode 1 – Retriggering the One-shot..........................................................................10-9