Intel 386

Intel386™ EX MICROPROCESSOR USER’S MANUAL
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FIGURES
Figure Page
13-7 SSIO Transmitter with Autotransmit Mode Disabled..................................................13-8
13-8 Transmit Data by Polling ............................................................................................13-9
13-9 Interrupt Service Routine for Transmitting Data Using Interrupts.............................13-10
13-10 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is High) .....13-11
13-11 Transmitter Master Mode, Single Word Transfer (Enabled when Clock is Low)......13-11
13-12 Receive Data by Polling ...........................................................................................13-13
13-13 Interrupt Service Routine for Receiving Data Using Interrupts.................................13-14
13-14 Receiver Master Mode, Single Word Transfer .........................................................13-15
13-15 Pin Configuration Register (PINCFG).......................................................................13-17
13-16 SIO and SSIO Configuration Register (SIOCFG).....................................................13-18
13-17 Clock Prescale Register (CLKPRS) .........................................................................13-19
13-18 SSIO Baud-rate Control Register (SSIOBAUD) .......................................................13-20
13-19 SSIO Baud-rate Count Down Register (SSIOCTR)..................................................13-21
13-20 SSIO Control 1 Register (SSIOCON1).....................................................................13-22
13-21 SSIO Control 2 Register (SSIOCON2).....................................................................13-23
13-22 SSIO Transmit Holding Buffer (SSIOTBUF).............................................................13-24
13-23 SSIO Receive Holding Buffer (SSIORBUF) .............................................................13-25
14-1 Channel Address Comparison Logic..........................................................................14-3
14-2 Determining a Channel’s Address Block Size............................................................14-4
14-3 Bus Cycle Length Adjustments for Overlapping Regions.........................................14-12
14-4 Pin Configuration Register (PINCFG).......................................................................14-15
14-5 Port 2 Configuration Register (P2CFG)....................................................................14-16
14-6 Chip-select High Address Register (CS
n ADH, UCSADH) .......................................14-17
14-7 Chip-select Low Address Register (CS
n ADL, UCSADL) .........................................14-18
14-8 Chip-select High Mask Registers (CS
n MSKH, UCSMSKH).....................................14-19
14-9 Chip-select Low Mask Registers (CS
n MSKL, UCSMSKL).......................................14-20
15-1 Refresh Control Unit Connections..............................................................................15-3
15-2 Refresh Clock Interval Register (RFSCIR).................................................................15-7
15-3 Refresh Control Register (RFSCON) .........................................................................15-8
15-4 Refresh Base Address Register (RFSBAD) ...............................................................15-9
15-5 Refresh Address Register (RFSADD) ......................................................................15-10
15-6 Connections to Ensure Refresh of All Rows in an 8-Bit Wide PSRAM Device ........15-11
15-7 RAS# Only Refresh Logic: Paged Mode ..................................................................15-13
15-8 RAS# Only Refresh Logic: Non-Paged Mode ..........................................................15-14
16-1 I/O Port Block Diagram...............................................................................................16-2
16-2 Logic Diagram of a Bi-directional Port........................................................................16-3
16-3 Port
n Configuration Register (P n CFG)......................................................................16-7
16-4 Port Direction Register (P
n DIR) .................................................................................16-8
16-5 Port Data Latch Register (P
n LTC)..............................................................................16-8
16-6 Port Pin State Register (P
n PIN) .................................................................................16-9
17-1 Watchdog Timer Unit Connections.............................................................................17-2
17-2 WDT Counter Value Registers (WDTCNTH and WDTCNTL)....................................17-8
17-3 WDT Status Register (WDTSTATUS)........................................................................17-9