Intel 386

xxiii
CONTENTS
TABLES
Table Page
13-2 Maximum and Minimum Baud-rate Output Frequencies............................................13-6
13-3 SSIO Registers.........................................................................................................13-16
14-1 CSU Signals .............................................................................................................14-13
14-2 CSU Registers..........................................................................................................14-14
15-1 RCU Signals...............................................................................................................15-4
15-2 RCU Registers ...........................................................................................................15-6
16-1 Pin Multiplexing ..........................................................................................................16-5
16-2 I/O Port Registers.......................................................................................................16-6
16-3 Control Register Values for I/O Port Pin Configurations.............................................16-7
17-1 WDT Signals ..............................................................................................................17-3
17-2 WDT Registers ...........................................................................................................17-7
18-1 Test Access Port Dedicated Pins ...............................................................................18-3
18-2 TAP Controller State Descriptions..............................................................................18-4
18-3 Example TAP Controller State Selections..................................................................18-5
18-4 Test-logic Unit Instructions.........................................................................................18-7
18-5 Boundary-scan Register Bit Assignments..................................................................18-9
A-1 Signal Description Abbreviations................................................................................. A-1
A-2 Description of Signals Available at the Device Pins.................................................... A-2
A-3 Pin State Abbreviations ............................................................................................... A-8
A-4 Pin States After Reset and During Idle, Powerdown, and Hold................................... A-9
D-1 Peripheral Register Addresses....................................................................................D-1
E-1 Instruction Set Summary ............................................................................................. E-2
E-2 Fields Within Instructions........................................................................................... E-23
E-3 Encoding of Operand Length (w) Field...................................................................... E-24
E-4 Encoding of reg Field When w Field is not Present in Instruction ............................. E-24
E-5 Encoding of reg Field When w Field is Present in Instruction ................................... E-25
E-6 Encoding of the Segment Register (sreg) Field......................................................... E-25
E-7 Encoding of 16-bit Address Mode with “mod r/m” Byte............................................. E-27
E-8 Encoding of 32-bit Address Mode with “mod r/m” Byte (No s-i-b Byte Present)........ E-28
E-9 Encoding of 32-bit Address Mode (“mod r/m” Byte and s-i-b Byte Present).............. E-29
E-10 Encoding of Operation Direction (d) Field ................................................................. E-30
E-11 Encoding of Sign-Extend (s) Field............................................................................. E-30
E-12 Encoding of Conditional Test (tttn) Field ................................................................... E-30
E-13 When Interpreted as Control Register Field .............................................................. E-31
E-14 When Interpreted as Debug Register Field............................................................... E-31
E-15 When Interpreted as Test Register Field................................................................... E-31