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Intel 386 User Manual

Intel 386
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13-11
SYNCHRONOUS SERIAL I/O UNIT
If the transmitter is disabled while a data value in the shift register is being shifted out, it continues
running until the last bit is shifted out. Then the shift register stops and the data and clock pins
(SSIOTX and STXCLK) are three-stated; the contents of the buffer register are not loaded into
the shift register.
If the transmitter is disabled then re-enabled before the current value has been shifted out, it con-
tinues as if it were never disabled.
If you enable the transmitter while the baud-rate generator clock is high, the data and clock pin
states are as shown in Figure 13-10. If you enable the transmitter while the baud-rate generator
clock is low, the data and clock pin states are as shown in Figure 13-11. These figures show master
mode, single word transfers. At the end of transmission, STXCLK and SSIOTX are three-stated
and require external pull-up resistors. For single word transfers, you must enable the transmitter,
which starts the shifting process, then disable the transmitter before 16 bits are shifted out. For
high baud rates use the Autotransmit mode.
Figure 13-10. Transmitter Master Mode, Single Word Transfer
(Enabled when Clock is High)
Figure 13-11. Transmitter Master Mode, Single Word Transfer
(Enabled when Clock is Low)
A2445-01
Baud-rate
Generator Clock
STXCLK
Transmitter Enable
TB15 TB13
SSIOTX
Float
Float
Float
Float
TB14 TB1 TB0
A2444-01
Baud-rate
Generator Clock
STXCLK
Transmitter Enable
TB15 TB14
SSIOTX
Float
Float
Float
Float
TB1 TB0

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Intel 386 Specifications

General IconGeneral
Architecturex86
Clock Speed12 MHz to 40 MHz
Transistor Count275, 000
Data Bus Width32-bit
Address Bus Width32-bit
Instruction Setx86
Introduced1985
Maximum Memory4 GB
Operating ModesReal mode, Protected mode, Virtual 8086 mode
MMUYes
Voltage5V
ModelIntel 386
PackagePGA
Process1.5 μm to 1 μm

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