134
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
Figure 67 depicts the SDQS to clock trace length matching diagram.
5.4.4.3 Data to Strobe Length Matching Requirements
The data bit signals SDQ[71:0] are grouped by byte lanes and associated with a data mask signal,
SDM[8:0], and a data strobe, SDQS[8:0]. The data and mask signals must be length matched to
their associated strobe within ± 25 mils, including package.
For DIMM0 this length matching includes the motherboard trace length to the pads of the DIMM0
connector (L1 + L2) plus package length.
For DIMM1, the motherboard trace length to the pads of the DIMM1connector (L1 + L2 + L3)
plus package length.
Length range formula for SDQ and SDM:
X = SDQS total length, including package length, as defined previously
Y = SDQ, SDM total length, including package length, within same byte lane, where
(X – 25 mils)
≤ Y ≤ (X + 25 mils)
Figure 67. SDQS to Clock Trace Length Matching Diagram
DIMM0
GMCH Package
855GME
Die
SDQS[8:0]
SCK[2:0]
SCK#[2:0]
Note: All lengths are measured from GMCH die-
pad to DIMM connector pad.
SDQS Length = Y0 , where
Clock Reference Length = X0
DIMM0 DIMM1
GMCH Package
SDQS[8:0]
SCK[5:3]
SCK#[5:3]
Clock Ref. Length = X1
Note: All lengths are measured from GMCH die-
pad to DIMM connector pad.
≤
≤
SDQS Length = Y1
(X1-1.5" )
≤
Y1
≤
( X1-0.5”)
855GME
Die
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