January 2007 207
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.5.1 AC’97 Audio Codec Detect Circuit and Configuration
Options
Table 80 provides general circuits to implement a number of different codec configurations. Please
refer to the
Communication Network Riser Specification, Revision 1.2, for Intel’s recommended
codec configurations
9.5.1.1 CNR 1.2 AC’97 Disable and Demotion Rules for the Motherboard
The following are the CNR 1.1/1.2 AC’97 Disable and Demotion Rules for the motherboard.
• All AC’97 Rev 2.2 codecs on the motherboard must always disable themselves when the
CDC_DN_ENAB# signal is in a high state.
• A motherboard AC’97 codec must never change its address or SDATA_IN line used,
regardless of the state of the CDC_DN_ENAB# signal.
• On a motherboard containing an AC’97 Controller supporting three AC’97 Codecs, the AC’97
Revision 2.2 codec on the motherboard must be connected to the SDATA_IN2 signal of the
CNR connector.
The above rules allow for forward and backward compatibility between CNR Version 1.1/1.2
cards. For more information on chaining consult the
Communication Network Riser Specification,
Revision 1.2
.
Figure 104. CNR Interface
Table 80. Signal Descriptions
Signal Description
CDC_DN_ENAB#
When low, indicates that the codec on the motherboard is enabled and primary on the
AC97 Interface. When high, indicates that the motherboard codec(s) must be removed
from the AC’97 Interface (held in reset), because the CNR codec(s) will be the primary
device(s) on the AC’97 Interface.
AC97_RESET# Reset signal from the AC’97 Digital Controller (6300ESB).
SDATA_IN
n
AC’97 serial data from an AC’97-compliant codec to an AC’97-compliant controller (i.e.,
the 6300ESB).
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