Intel 855GME

January 2007 41
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Design and Power Delivery Guidelines
4.1.2.1 Intel
®
Pentium
®
M/Celeron
®
M Processor Common Clock Signal
Package Length Compensation
Trace length matching for the common clock signals is not required. However, package
compensation for the common clock signals is required for the minimum board trace. Refer to
Table 4 and the example for more details. Package length compensation shall not be confused with
length matching. Length matching refers to constraints on the minimum and maximum length
bounds of a signal group based on clock length, whereas package length compensation refers to the
process of adjusting out package length variance across a signal group.
All common clock signals are required to meet the minimum pad-to-pad requirement of 2.212
inches, based on ADS# (as this signal has the longest package lengths) implies a minimum
pin-to-pin motherboard trace length of 1.0 inches or more depending on package lengths. As a
result, additional motherboard trace is added to some of the shorter common clock nets on the
system board in order to meet the longest common clock signal total trace lengths from the die-pad
of the processor to the associated die-pad of the chipset.
For example:
ADS# = 997 mils board trace + 454 Intel Pentium M/Celeron M Processor PKG + 761 GMCH
PKG = 2212 pad-to-pad length.
BR0# = X mils board trace + 465 Intel Pentium M/Celeron M Processor PKG + 336 GMCH PKG
= 2212 pad-to-pad length.
Therefore: BR0# board trace = 2212 pad-to-pad length - 465 Intel Pentium M/Celeron M Processor
PKG - 336 GMCH PKG = 1411 pin-to-pin length.
DBSY# DBSY# Strip-line 1159 6.5 55 ± 15% 4 and 8
DEFER# DEFER# Strip-line 1291 6.5 55 ± 15% 4 and 8
DPWR# DPWR# Strip-line 1188 6.5 55 ± 15% 4 and 8
DRDY# DRDY# Strip-line 1336 6.5 55 ± 15% 4 and 8
HIT# HIT# Strip-line 1303 6.5 55 ± 15% 4 and 8
HITM# HITM# Strip-line 1203 6.5 55 ± 15% 4 and 8
LOCK# HLOCK# Strip-line 1198 6.5 55 ± 15% 4 and 8
RS0# RS0# Strip-line 1315 6.5 55 ± 15% 4 and 8
RS1# RS1# Strip-line 1193 6.5 55 ± 15% 4 and 8
RS2# RS2# Strip-line 1247 6.5 55 ± 15% 4 and 8
TRDY# HTRDY# Strip-line 1312 6.5 55 ± 15% 4 and 8
RESET#
†
CPURESET# Strip-line 1101 6.5 55 ± 15% 4 and 8
Table 3. Intel
®
Pentium
®
M/Celeron
®
M Processor System Bus
Common Clock Signal Internal Layer Routing Guidelines (Sheet 2 of 2)
Signal Names
Transmission Line
Type
Total Trace Length
Nominal
Impedance
(Ω)
Width and
Spacing
(mils)
CPU GMCH
Min
(mils)
Max
(inches)
† For topologies where an ITP700FLEX debug port is implemented, refer to Section 4.1.6 for RESET#
(CPURESET#) implementation details.