January 2007 245
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
The circuit shown in Figure 136 may be implemented to control well isolation between the
VccSUS3.3 and RTC power-wells in the event that RSMRST# is not being actively asserted during
the discharge of the standby rail. Failure to implement this circuit or a circuit that functions similar
to this may result in excessive droop on the VCCRTC node during Sx-to-G3 power state transitions
(removal of AC power). Droop on this node may potentially cause the CMOS to be cleared or
corrupted, the RTC to lose time after several AC power cycles, or the intruder bit might assert
erroneously.
Figure 136. RTC Power Well Isolation Control
B2900-01
RSMRST#t
Intel
®
6300ESB
I/O Controller Hub
RSMRST#
generation
from GLUE4
or
equivalent
10 KΩ
empty
BAV99
BAV99
2.2 KΩ
MMBT3906
empty
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