January 2007 133
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
5.4.4.2 SDQS to Clock Length Matching Requirements
The first step in length matching is to determine the SDQS length range based on the SCK/SCK#
reference length defined previously. The total length of the SDQS strobe signals, including package
length, between the GMCH die-pad and the DIMMs must fall within the range defined in the
formulas below. Refer to the clock section for the definition of the clock reference length. Refer to
Table 32 for the definition of the various trace segments.
Length range formula for DIMM0:
X
0
= SCK[2:0]/SCK[2:0]# total reference length, including package length. Refer to Section 5.4.1
for more information.
Y
0
= SDQS[7:0] total length = GMCH package + L1 + L2, as shown in Figure 66, where:
(X
0
– 1.5”) ≤ Y
0
≤ (X
0
- 0.5”)
Length range formula for DIMM1:
X
1
= SCK[5:3]/SCK[5:3]# total reference length, including package length. Refer to Section 5.4.1
for more information.
Y
1
= SDQS[7:0] total length = GMCH package + L1 + L2 + L3, as shown in Figure 66 where:
(X
1
– 1.5”) ≤ Y
1
≤ (X
1
- 0.5”)
Length matching is only performed from the GMCH to the DIMMs, and does not involve the
length of L4, which may vary over its entire range. Intel recommends that routing segment length
L3 between DIMM0 to DIMM1 be held fairly constant and equal to the offset between clock
reference lengths X0 and X1. This produces the most straightforward length-matching scenario.
Note: A nominal SDQS package length of 700 mils may be used to estimate byte lane lengths prior to
performing package length compensation.
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