Intel 855GME User Manual

January 2007 133
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
5.4.4.2 SDQS to Clock Length Matching Requirements
The first step in length matching is to determine the SDQS length range based on the SCK/SCK#
reference length defined previously. The total length of the SDQS strobe signals, including package
length, between the GMCH die-pad and the DIMMs must fall within the range defined in the
formulas below. Refer to the clock section for the definition of the clock reference length. Refer to
Table 32 for the definition of the various trace segments.
Length range formula for DIMM0:
X
0
= SCK[2:0]/SCK[2:0]# total reference length, including package length. Refer to Section 5.4.1
for more information.
Y
0
= SDQS[7:0] total length = GMCH package + L1 + L2, as shown in Figure 66, where:
(X
0
– 1.5”) ≤ Y
0
≤ (X
0
- 0.5”)
Length range formula for DIMM1:
X
1
= SCK[5:3]/SCK[5:3]# total reference length, including package length. Refer to Section 5.4.1
for more information.
Y
1
= SDQS[7:0] total length = GMCH package + L1 + L2 + L3, as shown in Figure 66 where:
(X
1
– 1.5”) ≤ Y
1
≤ (X
1
- 0.5”)
Length matching is only performed from the GMCH to the DIMMs, and does not involve the
length of L4, which may vary over its entire range. Intel recommends that routing segment length
L3 between DIMM0 to DIMM1 be held fairly constant and equal to the offset between clock
reference lengths X0 and X1. This produces the most straightforward length-matching scenario.
Note: A nominal SDQS package length of 700 mils may be used to estimate byte lane lengths prior to
performing package length compensation.

Intel 855GME Specifications

General

Manufacturer	Intel
Model	855GME
Type	Chipset
Graphics Core	Intel Extreme Graphics 2
Memory Type	DDR
Maximum Memory Size	2 GB
FSB	400MHz
Integrated Video	Yes
Graphics Base Frequency	200 MHz
PCI Support	Yes
USB Support	USB 2.0
ATA Support	ATA-100
Package	Micro-FCBGA
Memory Types	DDR 200/266/333 MHz

Summary

3 General Design Considerations

3.1 Nominal Board Stack-Up

4 Intel® Pentium® M/Celeron® M Processor FSB Design and Power Delivery Guidelines

4.1 Intel® Pentium® M/Celeron® M Processor FSB Design Recommendations

Provides recommendations for meeting timing and voltage specs for optimal operation.

4.2 Intel System Validation Debug Support

4.3 Onboard Debug Port Routing Guidelines

4.4 Intel® Pentium® M/Celeron® M Processor Decoupling Recommendations

Offers guidelines for system board bulk and high-frequency decoupling capacitor solutions.

4.8 Intel 855GME Chipset Platform Power Delivery Guidelines

Provides guidelines for power delivery and decoupling for the Intel 855GME chipset.

5 System Memory Design Guidelines (DDR-SDRAM)

5.2 Length Matching and Length Formulas

5.4 Topologies and Routing Guidelines

6 Integrated Graphics Display Port

6.1 Analog RGB/CRT Guidelines

6.2 LVDS Transmitter Interface

6.3 Digital Video Out Port

7 AGP Port Design Guidelines

7.1 AGP Interface

7.2 AGP Routing Guidelines

Provides routing guidelines for AGP 1X and 2X/4X timing domains.

8 Hub Interface

8.1 8-Bit Hub Interface Routing Guidelines.

Covers routing guidelines for 8-bit Hub Interface data and strobe signals.

8.1.4 8-bit Hub Interface HIREF and HI_VSWING Generation/Distribution

9 Intel® 6300ESB Design Guidelines

9.1 Serial ATA Interface

9.6 USB 2.0

Covers layout guidelines for USB 2.0, including trace separation and connections.

9.7 Low Pin Count (LPC) Interface.

9.8 SMBus 2.0/SMLink Interface

9.10 PCI-X Design Guidelines

Provides guidelines for connecting and routing the 6300ESB PCI-X interface.

9.11 RTC

9.15 Power Management

11 Platform Clock Routing Guidelines

11.2 Clock Group Topologies and Routing Constraints

Defines recommended topologies and rules for platform level clocks.

12 Schematic Checklist Summary

12.1 Intel® Pentium® M/Celeron® M Processor Checklist

12.3 Intel® 855GME Chipset GMCH (82855GME) Checklist

Checklist for GMCH system memory interface and decoupling.

12.4 Intel® 6300ESB Checklist

Checklists for PCI-X, PCI, Hub, FWH/LPC, GPIO, USB, Power, CPU, System Management, RTC, UART, AC'97, Misc.

13 Layout Checklist

13.1 Processor Checklist

13.2 Intel® 855GME Chipset GMCH Layout Checklist

Layout checklist for GMCH interface signals and memory decoupling.

13.3 Intel® 6300ESB Layout Checklist

Provides layout guidelines for 8-bit Hub Interface, Serial ATA, IDE, USB 2.0, AC'97, RTC, PCI-X, PCI.