258
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
11.2.6 DOTCLK Clock Group
The 48 MHz DOTCLK is series terminated and routed point-to-point on the motherboard. This
clock operates independently and is not length-tuned to any other clock. Figure 143 depicts the
DOTCLK clock topology. Table 111 presents the DOTCLK clock routing constraints.
Figure 143. DOTCLK Clock Topology
Table 111. DOTCLK Clock Routing Constraints
Parameter Definition
Class Name DOTCLK
Class Type Individual Net
Topology Series Terminated Point to Point
Reference Plane Ground Referenced
Single Ended Trace Impedance (Zo) 55
Ω ±15%
Nominal Inner Layer Trace Width 4.0 mils
Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)
Minimum Spacing (See exceptions below.) 25 mils
Maximum Via Count 4
Series Termination Resistor Value 33
Ω ±5%
Trace Length Limits – L1 Up to 500 mils
Trace Length Limits – L2 2.0” to 8.0”
Total Length Range – L1 + L2 2.0” to 8.5”
Length Matching Required No
Breakout Exceptions 5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
NOTE: The DOTCLK is used internally by the GMCH to generate the pixel clock and must exhibit very low
jitter. Care should be taken to avoid routing through noisy areas and spacing rules should be
observed. Guard traces may be employed if necessary with ground stake vias on no less than
0.5- inch intervals.
L1
Rs
CK409
GMCH
L2
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