Intel 855GME

January 2007 297
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Schematic Checklist Summary
12.4.16 Power Checklist
Table 147. Power Checklist
Checklist Items Recommendations Reason/Impact
V
CC
3.3
Use twelve 0.1 µF and four 0.01 µF
decoupling caps
V
CC
1_5
Use six 0.1 µF and two 0.01 µF decoupling
caps
V
CC
Sus3.3
Use four 0.1 µF, one 0.01 µF, and one
1.0 µF decoupling cap
V
CC
Sus1_5 Use four 0.1 µF decoupling caps
V_CPU_IO
The power pins should be connected to the
proper power plane for the CPU's CMOS
Compatibility Signals. Use one 0.1 µF
decoupling cap.
V
CC
PLL Use three 0.1 µF decoupling caps
V
CC
HI Use two 0.1 µF decoupling caps
VCCREF Use one 1.0 µF decoupling cap
V5_REF
Use one 0.1 µF decoupling cap
V5REF is the reference voltage for 5 V
tolerant inputs in the 6300ESB. V5_REF
must power up before or simultaneous to
V
CC
3.3. It must power down after or
simultaneous to V
CC
3.3.
Proper connection ensures
functionality of system features
(i.e., USB 2.0)
V5_REF_Sus
Use one 0.1 µF decoupling cap
V5_REF_Sus is the reference voltage for 5
V tolerant inputs in the 6300ESB.
V5_REF_Sus
must power up before or
simultaneous to V
CC
Sus3.3. It must power
down after or simultaneous to V
CC
Sus3.3.
For most platforms this is not an issue
because V
CC
Sus3.3 is usually derived from
V5_REF_Sus.
Proper connection ensures
functionality of system features
(i.e., USB 2.0)
V
CC
RTC
Use two 0.1 µF decoupling caps, one close
to the 6300ESB, and one close to the
battery.
No clear CMOS jumper on V
CC
RTC. Use a
jumper on RTCRST# or a GPI, or use a safe
mode strapping for Clear CMOS
VCCA Use one 0.1 µF decoupling cap