Intel 855GME User Manual

256
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
11.2.4 PCI Clock Group
The PCI clocks are series terminated and routed point-to-point as on the motherboard between the
CK409 and the PCI connectors with dedicated buffers for of the three slots. These clocks are
synchronous to the CLK33 clocks and are length tuned to compensate for the segment on the PCI
daughtercard. Figure 141 depicts the PCI clock group topology. Table 109 presents the PCICLK
clock group routing constraints.
Figure 141. PCI Clock Group Topology
Table 109. PCICLK Clock Group Routing Constraints
Parameter Definition
Class Name PCICLK
Class Type Individual Nets
Topology Series Terminated Point to Point
Reference Plane Ground Referenced
Single Ended Trace Impedance (Zo) 55
Ω ±15%
Nominal Inner Layer Trace Width 4.0 mils
Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)
Minimum Spacing (See exceptions below.) 20 mils
Serpentine Spacing 20 mils
Maximum Via Count 4
Series Termination Resistor Value 33
Ω ±5%
Trace Length Limits – L1 Up to 500 mils (breakout segment)
Trace Length Limits – L2 1.5” to 8.0”
Trace Length Limits – L3 2.5” (as per PCI specification)
Total Length Range – L1 + L2 CLK33 – 2.5” (for nominal matching)
Length Matching Required Yes (Pin to Pin)
Clock to Clock Length Matching
±2.0”
PCICLK to PCICLK to (CLK33 – 2.5”)
Breakout Region Exceptions
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
Rs
CK409 PCI Device
L2
PCI
Connector
Trace on Card
L3 L1

Intel 855GME Specifications

General

Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English