January 2007 263
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
11.2.9.2 SRC General Routing Guidelines
• When routing the 100 MHz differential clocks, do not split up the two halves of a differential
clock pair between layers. Route to all agents on the same physical routing layer referenced to
ground.
• If a layer transition is required, make sure skew induced by the vias used to transition between
routing layers is compensated in the traces to other agents.
• Do not place vias between adjacent complementary clock traces, and avoid differential vias.
Vias placed in one half of a differential pair must be matched by a via in the other half.
Differential vias may be placed within length L1, between clock driver and Rs, if needed to
shorten length L1.
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