EasyManua.ls Logo

Intel 855GME

Intel 855GME
320 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
308
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
SDQ[71:0]
SDM[8:0]
SDQS[8:0]
See a detailed discussion on this topic in
Section 5.4.4
Route SDQ/SDM with trace impedance
55
Ω ± 15% using 2:1 spacing.
Route SDQS strobes similarly with 3:1
spacing.
Isolation from non-DDR signals should be
20 mils.
Overall min/max length to the DIMM must
comply with clock length matching
requirements.
The full data bus SDQ[63:0], mask bus
SDM[7:0], and strobe signals SDQS[7:0]
should be routed on the same internal
signal layer.
It is required that the SDQ byte group and
the associated SDM and SDQS signals
within a byte lane be routed on the same
internal layer.
Maximum recommended via count per
signal is 6.
Refer to the detailed routing
guidelines in Section 5.4.4.
SCKE[3:0]
SCS[3:0]#
See a detailed discussion on this topic in
Section 5.4.5
Route with trace impedance 55
Ω ± 15%
using 2:1 spacing.
Isolation from non-DDR signals should be
20 mils.
GMCH pad to DIMM trace length limits are
2 to 6 inches.
Place parallel termination resistor within 2
inches of DIMM pad.
Overall min/max length to the DIMM must
comply with clock length matching
requirements.
Maximum recommended via count per
signal is 3.
Refer to the detailed routing
guidelines in Section 5.4.5.
SRAS#
SCAS#
SWE#
SMA[12:6,3,0]
SBA[1:0]
See a detailed discussion on this topic in
Section 5.4.6.
Route with trace impedance 55
Ω ± 15%
using 2:1 spacing.
Isolation from non-DDR signals should be
20 mils.
GMCH pad to first DIMM trace length
limits are 2 to 5.5 inches.
Total DIMM to DIMM spacing should be
less than 2 inches.
Place parallel termination resistor within
1.5 inches of the second DIMM pad.
Overall min/max length to the DIMM must
comply with clock length matching
requirements.
Maximum recommended via count per
signal is 6.
Refer to the detailed routing
guidelines in Section 5.4.6.
Table 149. Intel
®
855GME Chipset GMCH Layout Checklist (Sheet 2 of 6)
Checklist Items Recommendations Comments

Table of Contents

Related product manuals