138
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
5.4.5 Control Signals – SCKE[3:0], SCS[3:0]#
The 82855GME control signals, SCKE[3:0] and SCS[3:0]#, are clocked into the DDR SDRAM
devices using clock signals SCK[5:0]/SCK[5:0]#. The GMCH drives the control and clock signals
together, with the clocks crossing in the valid control window. The GMCH provides one chip select
(CS) and one clock enable (CKE) signal per DIMM physical device row. Two chip select and two
clock enable signals are routed to each DIMM. Refer to Table 35 for the CKE and CS# signal to
DIMM mapping.
The control signal routing shall transition from an external layer to an internal signal layer under
the GMCH, keep to the same internal layer until transitioning back out to an external layer to
connect to the appropriate pad of the DIMM connector and the parallel termination resistor. When
the layout requires additional routing before the termination resistor, return to the same internal
layer and transition back out to an external layer immediately prior to parallel termination resistor.
SDQ[67] AG16 530
SDQ[68] AH14 701
SDQ[69] AE15 421
SDQ[70] AF16 491
SDQ[71] AF17 530
SDQS[0] AG2 925 SDM[0] AE5 838
SDQS[1] AH5 838 SDM[1] AE6 693
SDQS[2] AH8 756 SDM[2] AE9 538
SDQS[3] AE12 466 SDM[3] AH12 606
SDQS[4] AH17 678 SDM[4] AD19 492
SDQS[5] AE21 487 SDM[5] AD21 470
SDQS[6] AH24 770 SDM[6] AD24 557
SDQS[7] AH27 858 SDM[7] AH28 917
SDQS[8] AD15 418 SDM[8] AH15 685
Table 34. DDR SDQ/SDM/SDQS Package Lengths (Sheet 2 of 2)
Signal Pin Number
Pkg Length
(mils)
Signal Pin Number
Pkg Length
(mils)
Table 35. Control Signal to DIMM Mapping
Signal Relative To DIMM Pin
SCS[0]# DIMM0 AD23
SCS[1]# DIMM0 AD26
SCS[2]# DIMM1 AC22
SCS[3]# DIMM1 AC25
SCKE[0] DIMM0 AC7
SCKE[1] DIMM0 AB7
SCKE[2] DIMM1 AC9
SCKE[3] DIMM1 AC10
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