Intel 855GME User Manual

100
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.4.4 Processor and GMCH VCCP Voltage Plane and Decoupling
The 400 MHz high-frequency operation of the Intel Pentium M/Celeron M processor and
82855GME’s Intel Pentium M/Celeron M processor FSB requires careful attention to the design of
the power delivery for VCCP (1.05 V) to the Intel Pentium M/Celeron M processor and GMCH.
Refer to Table 22 that presents and summarizes the VCCP voltage rail decoupling requirements.
Two 150 µF POSCAPs with an ESR of 42 m
Ω shall be used for bulk decoupling. The
recommendation is to place each POSCAP on the secondary side of the motherboard to minimize
inductance.
• One capacitor shall be placed next to the Intel Pentium M/Celeron M processor socket.
• One capacitor shall be placed in close proximity to the GMCH package.
• Ten 0.1 µF X7R capacitors in a 0603 form factor shall be placed on the secondary side of the
motherboard under the Intel Pentium M/Celeron M processor socket cavity next to the VCCP
pins of the Intel Pentium M/Celeron M processor.
• Four capacitors shall be spread out near the data and address signal sides.
• Two capacitors shall be placed on the legacy signal side of the Intel Pentium M/Celeron M
processor socket’s pin-map.
• The Intel Pentium M/Celeron M processor and GMCH VCCP pins shall be shorted with a
wide, VCCP plane, preferably on the secondary side such that it extends across the whole
shadow of the Intel Pentium M/Celeron M processor FSB signals routed between the Intel
Pentium M/Celeron M processor and 82855GME. The 1.05 volt VR feed point into the VCCP
plane shall be roughly between the Intel Pentium M/Celeron M processor and 82855GME.
Figure 47. Recommended SP Cap Via Connection Layout (Secondary Side Layer)
50 mils
VCC-CORE
GND
6
6 mils
228 mils
50 m
ils
50 mils
VCC-CORE
GND
6
6 mils
228 mils
50 m
ils

Intel 855GME Specifications

General

Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English