January 2007 35
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
General Design Considerations
3.2 Alternate Stack-Ups
Designers may choose to use different stack-ups (number of layers, thickness, trace width, etc.)
from the one example outlined in Figure 2. However, the following key elements shall be observed:
1. Final post lamination, post etching, and post plating dimensions shall be used for electrical
model extractions.
2. Power plane layers shall be 1 oz. thick and the outer signal layers shall be ½ oz. thick, while
the internal signal layers shall be 1 oz. thick. External layers become 1 – 1.5 oz. (1.2 – 2 mils)
thick after plating.
3. All high-speed signals shall reference solid ground planes through the length of their routing
and shall not cross plane splits. To ensure this, both planes surrounding strip-lines shall be
GND.
4. Intel recommends that high-speed signal routing be done on internal, strip-line layers.
5. For high-speed signals transitioning between layers next to the component, the signal pins
shall be accounted for by the GND stitching vias that would stitch all the GND plane layers in
that area of the motherboard. Due to the arrangement of the Intel Pentium M/Celeron M
Processor and Intel 855GME chipset Graphics Memory Controller Hub (82855GME)
pin-maps, GND vias placed near all GND lands are also very close to high-speed signals that
may be transitioning to an internal layer. Thus, no additional ground stitching vias (besides the
GND pin vias) are required in the immediate vicinity of the Intel Pentium M/Celeron M
Processor and 82855GME packages to accompany the signal transitions from the component
side into an internal layer.
6. High-speed routing on external layers shall be minimized in order to avoid EMI. Routing on
external layers also introduces different delays compared to internal layers. This makes it
extremely difficult to do length matching when some routing is done on both internal and
external layers.
7. When Intel’s recommended stackup guidelines are not used, the designer is liable for all
aspects of their board design (i.e., understanding impacts of SI and power distribution).
To Next Page
Loading...
Need help?
General
