17
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
42 CPC Group Package Lengths ..................................................................................................150
43 Recommended GMCH DAC Components ...............................................................................156
44 Signal Group and Signal Pair Names.......................................................................................158
45 LVDS Signal Trace Length Matching Requirements ................................................................159
46 LVDS Signal Group Routing Guidelines...................................................................................160
47 LVDS Package Lengths............................................................................................................161
48 DVO Interface Signal Groups...................................................................................................162
49 AGP/DVO Pin Muxing...............................................................................................................163
50 DVO Interface Trace Length Mismatch Requirements.............................................................164
51 DVOB and DVOC Routing Guideline Summary .......................................................................165
52 DVOB Interface Package Lengths............................................................................................165
53 DVOC Interface Package Lengths............................................................................................166
54 Allowable Interconnect Skew Calculation.................................................................................168
55 DVO Enabled Routing Guideline Summary..............................................................................169
56 GMBUS Pair Mapping and Options..........................................................................................170
57 AGP 2.0 Signal Groups ............................................................................................................174
58 AGP 2.0 Data/Strobe Associations...........................................................................................174
59 Layout Routing Guidelines for AGP 1X Signals........................................................................175
60 Layout Guidelines for AGP 2x/4x Signals.................................................................................176
61 AGP 2.0 Data Lengths Relative to Strobe Length ....................................................................177
62 AGP 2.0 Routing Guideline Summary......................................................................................177
63 AGP Interface Package Lengths ..............................................................................................178
64 AGP Pull-Up/Pull-Down Requirements and Straps ..................................................................180
65 AGP 2.0 Pull-up Resistor Values..............................................................................................181
66 Hub Interface 1.5 Data Signals Routing Summary...................................................................183
67 Hub Interface 1.5 Strobe Signals Routing Summary................................................................184
68 8-Bit Hub Interface HIREF/HI_VSWING Generation Circuit Specifications..............................184
69 Recommended Resistor Values for Single VREF/VSWING Divider Circuit .............................188
70 Recommended Resistor Values for HLVREF and PSWING Divider Circuits for GMCH..........188
71 Hub Interface RCOMP Resistor Values....................................................................................189
72 SATA Routing Summary...........................................................................................................192
73 SATA BIAS Routing Summary .................................................................................................193
74 IDE Signal Groups ....................................................................................................................194
75 IDE Routing Summary..............................................................................................................194
76 AC’97 AC_BIT_CLK Routing Summary....................................................................................201
77 AC’97 AC_SDOUT/AC_SYNC Routing Summary....................................................................202
78 AC’97 AC_SDIN Routing Summary..........................................................................................203
79 Supported Codec Configurations..............................................................................................205
80 Signal Descriptions...................................................................................................................207
81 CNR Routing Summary ............................................................................................................209
82 USB BIAS Routing Summary ...................................................................................................212
83 USB 2.0 Back Panel Trace Length Guidelines (Common-mode Choke, 55 Ω ± 10%) ............212
84 USB 2.0 CNR Trace Length Guidelines (Common-mode Choke, 55 Ω ± 10%).......................213
85 USB 2.0 Front Panel Trace Length Guidelines (Common-mode Choke, 55 Ω ± 10%)............213
86 Conductor Resistance (Table 6-6 from USB 2.0 Specification)................................................216
87 Front Panel Header Pin-Out .....................................................................................................217
88 LPC Interface Routing Summary..............................................................................................221
89 Bus Capacitance Reference Chart ...........................................................................................224
90 Bus Capacitance/Pull-Up Resistor Relationship.......................................................................224
91 PCI Data Signals Routing Summary.........................................................................................226
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