January 2007 273
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Schematic Checklist Summary
SDQS8
56
Ω pull-up to
V_1P25_MEMVTT
10
Ω
When ECC support is not implemented,
SDQ[71:64], SDM8, and SDQS8 shall be
left as NC. For ECC support, these signals
connect to DIMMs.
SMA[12:6,3,0]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0 and DIMM 1.
SMA[5,4,2,1]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0.
SMAB[5,4,2,1]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 1.
SCK0, SCK0#
SCK1, SCK1#
These clock signals route differentially
directly to DIMM 0.
Alternatively, refer to Section 5.5.1 for
information regarding GMCH clock routing
flexibility.
SCK2, SCK2#
Route these signals differentially directly
to DIMM 0.
Alternatively, refer to Section 5.5.1 for
information regarding GMCH clock routing
flexibility.
SCK3, SCK3#
SCK4, SCK4#
These clock signals route differentially
directly to DIMM 0.
Alternatively, refer to Section 5.5.1 for
information regarding GMCH clock routing
flexibility.
SCK5, SCK5#
Route these signals differentially directly
to DIMM 1.
Alternatively, refer to Section 5.5.1 for
information regarding GMCH clock routing
flexibility.
SMVREF_0
Resistor divider to
V_2P5_SM consists of two
identical resistors
(50
Ω − 150 Ω 1%)
Signal voltage level = V_2P5_SM/2.
Optionally, the Intel CRB may support a
buffer to provide the necessary current
and reference voltage to SMVREF.
Refer to Figure 150.
Place a 0.1 µF cap by GMCH, DIMM 0,
and DIMM 1 pins. Refer to Section 4.8.2.2
for more information.
SMVSWINGL
604
Ω 1% pull-up to
V_2P5_SM
150
Ω 1% pull-down to
GND
Signal voltage level = 1/5 * V_2P5_SM.
Need 0.1 µF cap at the GMCH pin.
SMVSWINGH
150
Ω 1% pull-up to
V_2P5_SM
604
Ω 1% pull-down to
GND
Signal voltage level = 4/5 * V_2P5_SM.
Need 0.1 µF cap at the GMCH pin.
SMRCOMP
60.4
Ω 1% pull-up to
V_2P5_SM
60.4
Ω 1% pull-down to
GND
Signal voltage level = 1/2 * V_2P5_SM.
Need 0.1 µF cap between V_2P5_SM and
GND near the voltage divider.
Table 121. GMCH System Memory Interface Checklist (Sheet 2 of 2)
Pin Name
System
Pull-up/Pull-down
Series
Resistor
Notes √