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NXP Semiconductors MPC5777C Reference Manual
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MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
2
Freescale Semiconductor, Inc.
1
3
Table of Contents
Default Chapter
3
Table of Contents
3
Chapter 1
7
Overview
7
Device Versions
7
Audience
8
Document Organization
8
Conventions
8
Numbering Systems
8
Typographic Notation
9
Special Terms
9
References
10
Chapter 2 Platform Configuration Module (PCM)
11
PCM Memory Map and Register Descriptions
11
FEC Burst Optimization Master Control Register (PCM_FBOMCR)
12
Bus Bridge Configuration Register 1 (PCM_IAHB_BE1)
13
Bus Bridge Configuration Register 2 (PCM_IAHB_BE2)
16
Chapter 3 Modular CAN (M_CAN)
19
Chip-Specific M_CAN Information
19
M_CAN Message RAM Allocation
19
Introduction
19
Functional Description
20
External Signals
22
Overview
23
Features
23
Block Diagram
25
Dual Clock Sources
26
Dual Interrupt Lines
26
Memory Map and Register Description
27
Core Release Register (M_CAN_CREL)
28
Endian Register (M_CAN_ENDN)
29
Fast Bit Timing and Prescaler Register (M_CAN_FBTP)
30
Test Register (M_CAN_TEST)
32
RAM Watchdog Register (M_CAN_RWD)
33
CC Control Register (M_CAN_CCCR)
34
Bit Timing and Prescaler Register (M_CAN_BTP)
36
Timestamp Counter Configuration Register (M_CAN_TSCC)
38
Timestamp Counter Value Register (M_CAN_TSCV)
38
Timeout Counter Configuration Register (M_CAN_TOCC)
39
Timeout Counter Value Register (M_CAN_TOCV)
40
Error Counter Register (M_CAN_ECR)
41
Protocol Status Register (M_CAN_PSR)
42
Interrupt Register (M_CAN_IR)
45
Interrupt Enable Register (M_CAN_IE)
49
Interrupt Line Select Register (M_CAN_ILS)
52
Interrupt Line Enable Register (M_CAN_ILE)
55
Global Filter Configuration Register (M_CAN_GFC)
56
Standard ID Filter Configuration Register (M_CAN_SIDFC)
57
Extended ID Filter Configuration Register (M_CAN_XIDFC)
58
Extended ID and Mask Register (M_CAN_XIDAM)
59
High Priority Message Status Register (M_CAN_HPMS)
59
New Data 1 Register (M_CAN_NDAT1)
60
New Data 2 Register (M_CAN_NDAT2)
61
Rx FIFO 0 Configuration Register (M_CAN_RXF0C)
61
Rx FIFO 0 Status Register (M_CAN_RXF0S)
62
Rx FIFO 0 Acknowledge Register (M_CAN_RXF0A)
63
Rx Buffer Configuration Register (M_CAN_RXBC)
64
Rx FIFO 1 Configuration Register (M_CAN_RXF1C)
64
Rx FIFO 1 Status Register (M_CAN_RXF1S)
65
Rx FIFO 1 Acknowledge Register (M_CAN_RXF1A)
66
Rx Buffer / FIFO Element Size Configuration Register (M_CAN_RXESC)
67
Tx Buffer Configuration Register (M_CAN_TXBC)
69
Tx Fifo/Queue Status Register (M_CAN_TXFQS)
70
Tx Buffer Element Size Configuration (M_CAN_TXESC)
71
Tx Buffer Request Pending Register (M_CAN_TXBRP)
72
Tx Buffer Add Request Register (M_CAN_TXBAR)
73
Tx Buffer Cancellation Request Register (M_CAN_TXBCR)
73
Tx Buffer Transmission Occurred Register (M_CAN_TXBTO)
74
Tx Buffer Cancellation Finished Register (M_CAN_TXBCF)
74
Tx Buffer Transmission Interrupt Enable Register (M_CAN_TXBTIE)
75
Tx Buffer Cancellation Finished Interrupt Enable Register (M_CAN_TXBCIE)
75
Tx Event FIFO Configuration Register (M_CAN_TXEFC)
76
Tx Event FIFO Status Register (M_CAN_TXEFS)
77
Tx Event FIFO Acknowledge Register (M_CAN_TXEFA)
78
Message RAM
78
Rx Buffer and FIFO Element
79
Tx Buffer Element
81
Tx Event FIFO Element
83
Standard Message ID Filter Element
84
Extended Message ID Filter Element
85
Functional Description
87
Operating Modes
87
Timestamp Generation
97
Timeout Counter
97
Rx Handling
98
Tx Handling
108
FIFO Acknowledge Handling
114
Interface to DMA Controller
115
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NXP Semiconductors MPC5777C Specifications
General
Brand
NXP Semiconductors
Model
MPC5777C
Category
Motherboard
Language
English
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