NXP Semiconductors MPC5777C Reference Manual

3.3.43 Tx Event FIFO Configuration Register (M_CAN_TXEFC)
Address: 0h base + F0h offset = F0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
EFWM
0
EFS EFSA
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M_CAN_TXEFC field descriptions
Field Description
0–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2–7
EFWM
Event FIFO Watermark
NOTE: This field has Protected Write status.
0 Watermark interrupt disabled
1-32 Level for Tx Event FIFO watermark interrupt (IR[TEFW])
>32 Watermark interrupt disabled
8–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–15
EFS
Event FIFO Size
The Tx Event FIFO elements are indexed from 0 to EFS - 1
NOTE: This field has Protected Write status.
0 Tx Event FIFO disabled
1-32 Number of Tx Event FIFO elements
>32 Values greater than 32 are interpreted as 32
16–29
EFSA
Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM (32-bit word address, Message RAM).
NOTE: This field has Protected Write status.
30–31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Memory Map and Register Description
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
76 Freescale Semiconductor, Inc.

NXP Semiconductors MPC5777C Specifications

General

Brand	NXP Semiconductors
Model	MPC5777C
Category	Motherboard
Language	English