The arbiter has a pseudo address pre-fetching mechanism that allows the data of the
previous access to overlap with the address of the current access. The pseudo address pre-
fetching scheme saves multiple clock cycles when there are multiples accesses to the
external Message RAM.
3.1.3.1.2 ECC Controller
The ECC Controller provides Single Error Correction / Double Error Detection
(SECDED). It guarantees single bit error correction and double bit error detection
(without correction). The SECDED code is not guaranteed to detect more than two bits
with error.
Each 32 data bits of the external Message RAM is associated with 7 ECC bits. If all these
39 bits are zero or one, then it is flagged as non-correctable error.
For writes to the external Message RAM, the ECC bits (7-bit) are calculated using the
data bits (32-bit). The data bits plus ECC bits (39-bit) are written into the specified
memory address. The error detection and correction are performed on the reads from the
external Message RAM.
When an M_CAN accesses the external Message RAM, the ECC bits are calculated by
the ECC Controller and they are sent to this M_CAN.
3.1.3.2 External Message RAM
The external Message RAM supports only 32-bit write and read accesses.
The CPU can access the external Message RAM through the M_CAN subsystem. In this
case, the CPU can do 8/16/32-bit read accesses to the external Message RAM.
3.1.3.3 Transfer Error
The M_CAN subsystem does not report any transfer error.
3.1.4 External Signals
The M_CAN subsystem external signals are shown in the following table.
Chip-specific M_CAN information
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
22 Freescale Semiconductor, Inc.
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