NXP Semiconductors MPC5777C - Rx FIFO 1 Status Register (MCANRXF1 S)

M_CAN_RXF1C field descriptions (continued)
Field Description
0 FIFO 1 blocking mode
1 FIFO 1 overwrite mode
1–7
F1WM
Rx FIFO 1 Watermark
NOTE: This field has Protected Write status.
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 1 watermark interrupt (IR[RF1W])
>64 Watermark interrupt disabled
8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–15
F1S
Rx FIFO 1 Size
The Rx FIFO 1 elements are indexed from 0 to F1S - 1.
NOTE: This field has Protected Write status.
0 No Rx FIFO 1
1-64 Number of Rx FIFO 1 elements
>64 Values greater than 64 are interpreted as 64
16–29
F1SA
Rx FIFO 1 Start Address
Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Message RAM).
NOTE: This field has Protected Write status.
30–31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3.3.30 Rx FIFO 1 Status Register (M_CAN_RXF1S)
Address: 0h base + B4h offset = B4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DMS 0 RF1L F1F 0 F1PI
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved F1GI 0 F1FL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M_CAN_RXF1S field descriptions
Field Description
0–1
DMS
Debug Message Status
Table continues on the next page...
Chapter 3 Modular CAN (M_CAN)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 65