NXP Semiconductors MPC5777C - Rx Buffer FIFO Element Size Configuration Register (MCANRXESC)

M_CAN_RXF1A field descriptions (continued)
Field Description
26–31
F1AI
Rx FIFO 1 Acknowledge Index
After the CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer
index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S[F1GI]
to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL].
3.3.32 Rx Buffer / FIFO Element Size Configuration Register
(M_CAN_RXESC)
Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO element. Data
field sizes >8 bytes are intended for CAN FD operation only.
NOTE
In case the data field size of an accepted CAN frame exceeds
the data field size configured for the matching Rx Buffer or Rx
FIFO, only the number of bytes as configured by RXESC are
stored to the Rx Buffer resp. Rx FIFO element. The rest of the
frame’s data field is ignored.
Address: 0h base + BCh offset = BCh
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
RBDS
0
F1DS
0
F0DS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M_CAN_RXESC field descriptions
Field Description
0–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21–23
RBDS
Rx Buffer Data Field Size
NOTE: This field has Protected Write status.
000 8 byte data field
001 12 byte data field
010 16 byte data field
011 20 byte data field
100 24 byte data field
Table continues on the next page...
Chapter 3 Modular CAN (M_CAN)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 67