NXP Semiconductors MPC5777C - Rx Buffer Configuration Register (MCANRXBC); Rx FIFO 1 Configuration Register (MCANRXF1 C)

3.3.28 Rx Buffer Configuration Register (M_CAN_RXBC)
Address: 0h base + ACh offset = ACh
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
RBSA
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M_CAN_RXBC field descriptions
Field Description
0–15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16–29
RBSA
Rx Buffer Start Address
Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). Also
used to reference debug messages A, B, C.
NOTE: This field has Protected Write status.
30–31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3.3.29 Rx FIFO 1 Configuration Register (M_CAN_RXF1C)
Address: 0h base + B0h offset = B0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
F1OM
F1WM
0
F1S
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
F1SA
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M_CAN_RXF1C field descriptions
Field Description
0
F1OM
FIFO 1 Operation Mode
FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs).
NOTE: This field has Protected Write status.
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Memory Map and Register Description
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
64 Freescale Semiconductor, Inc.