NXP Semiconductors MPC5777C - Endian Register (MCANENDN)

REL STEP SUBSTEP YEAR MON DAY Release
0 2 0 9 3 26 Revision 0.2.0, date 2009/03/26
Address: 0h base + 0h offset = 0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
REL STEP SUBSTEP YEAR MON DAY
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
The coding of revisions depends on the module version used in the device.x = Undefined at reset.•
M_CAN_CREL field descriptions
Field Description
0–3
REL
Core Release
One digit, BCD-coded.
4–7
STEP
Step of Core Release
One digit, BCD-coded.
8–11
SUBSTEP
Sub-step of Core Release
One digit, BCD-coded.
12–15
YEAR
Time Stamp Year
One digit, BCD-coded.
16–23
MON
Time Stamp Month
Two digits, BCD-coded.
24–31
DAY
Time Stamp Day
Two digits, BCD-coded.
3.3.2 Endian Register (M_CAN_ENDN)
Address: 0h base + 4h offset = 4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ETV
W
Reset
1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1
Chapter 3 Modular CAN (M_CAN)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 29