NXP Semiconductors MPC5777C - RAM Watchdog Register (MCANRWD)

M_CAN_TEST field descriptions (continued)
Field Description
0 The CAN bus is dominant (M_CAN Rx = 0)
1 The CAN bus is recessive (M_CAN Rx = 1)
25–26
TX
Control of Transmit Pin
NOTE: This field has Protected Write status.
00 Reset value, M_CAN Tx is controlled by the M_CAN, updated at the end of the CAN bit time
01 Sample Point can be monitored at M_CAN Tx
10 Dominant (0) level at M_CAN Tx
11 Recessive (1) at M_CAN Tx
27
LBCK
Loopback mode
NOTE: This field has Protected Write status.
0 Reset value, Loopback mode is disabled
1 Loopback mode is enabled (see Test Modes)
28–31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3.3.5 RAM Watchdog Register (M_CAN_RWD)
The RAM Watchdog monitors when the Message RAM output is available to M_CAN.
When the M_CAN requests a Message RAM access, M_CAN starts the Message RAM
Watchdog Counter with the value configured by the RWD[WDC]. The counter is
reloaded with RWD[WDC] when the M_CAN request to Message RAM is successful
completed. In case there is no response from the Message RAM until the counter has
counted down to zero, the counter stops and interrupt flag IR[WDI] is set.
Address: 0h base + 14h offset = 14h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 WDV
WDC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M_CAN_RWD field descriptions
Field Description
0–15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 3 Modular CAN (M_CAN)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 33