3.3.45 Tx Event FIFO Acknowledge Register (M_CAN_TXEFA)
Address: 0h base + F8h offset = F8h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
EFAI
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M_CAN_TXEFA field descriptions
Field Description
0–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–31
EFAI
Event FIFO Acknowledge Index
After the CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the
index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index
TXEFS[EFGI] to EFAI + 1 and update the Event FIFO Fill Level TXEFS[EFFL].
3.4 Message RAM
For storage of Rx/Tx messages and for storage of the filter configuration a single- or
dual-ported Message RAM must be connected to the M_CAN module.
The Message RAM has a width of 32 bits. In case parity checking or ECC is used, a
corresponding number of bits must be added to each word.
When operated in CAN FD mode, the required Message RAM size strongly depends on
the element size configured for Rx FIFO0, Rx FIFO1, Rx Buffers, and Tx Buffers via
RXESC[F0DS], RXESC[F1DS], RXESC[RBDS], and TXESC[TBDS], respectively.
The M_CAN module can be configured to allocate up to 4352 words in the Message
RAM. For the actual amount of Message RAM on this chip, see the chip-specific
M_CAN information.
It is not necessary to configure each of the sections listed in the following figure, and
there is no restriction with respect to the sequence of the sections.
Message RAM
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
78 Freescale Semiconductor, Inc.
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