NXP Semiconductors MPC5777C - Reset Circuitry on Daughter Card; MCU External Clock Circuit

• 50% bandwidth for CPU accesses to the external Message RAM. The CPU does not
wait for more than one clock cycle to access the external Message RAM (see
examples 1 and 3).
• 50% bandwidth is shared between M_CAN_0 and M_CAN_1 accesses to the
external Message RAM. Each M_CAN waits at least one clock cycle to access the
external Message RAM (see examples 1, 2, and 3).
• If there is no CPU request, all bandwidth is distributed to M_CAN_0 and M_CAN_1
(see example 2).
• If there are no M_CAN_0 and M_CAN_1 requests, all bandwidth is distributed to the
CPU.
• If there are requests from only one M_CAN, the other M_CAN's bandwidth is
distributed to the first M_CAN (see example 1).
The following examples illustrate the dynamic arbiter scheme.
• Example 1: The following figure shows who accesses the external Message RAM
when only CPU and M_CAN_0 try to access to it.
CPU
M_CAN_0
CPU
M_CAN_0
CPU
M_CAN_0
CPU
M_CAN_0
CPU clock
who accesses the
external Message RAM
• Example 2: The following figure shows who accesses the external Message RAM
when only M_CAN_0 and M_CAN_1 try to access to it.
M_CAN_1 M_CAN_1 M_CAN_1 M_CAN_1
CPU clock
who accesses the
external Message RAM
M_CAN_0 M_CAN_0 M_CAN_0 M_CAN_0
• Example 3: The following figure shows who accesses the external Message RAM
when the CPU, M_CAN_0, and M_CAN_1 try to access to it.
CPU
M_CAN_0
CPU
M_CAN_1
CPU
M_CAN_0
CPU
M_CAN_1
CPU clock
who accesses the
external Message RAM
The read or write accesses to the external Message RAM use two clock cycles. In the first
clock cycle, the address is available, and in the second, the data is available.
Chapter 3 Modular CAN (M_CAN)
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
Freescale Semiconductor, Inc. 21