• AUTOSAR optimized
• SAE J1939 optimized
• Improved acceptance filtering
• Two configurable Receive FIFOs
• Separate signalling on reception of High Priority Messages
• Up to 64 dedicated Receive Buffers
• Up to 32 dedicated Transmit Buffers
• Configurable Transmit FIFO
• Configurable Transmit Queue
• Configurable Transmit Event FIFO
• Direct Message RAM access for Host CPU
• Multiple M_CANs may share the same Message RAM
• Programmable loop-back test mode
• Maskable module interrupts
• 8/16/32-bit Generic Slave Interface for connection customer-specific Host CPUs
• Two clock domains (CAN clock and Host clock)
• Power-down support
• Debug on CAN support
Overview
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
24 Freescale Semiconductor, Inc.
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