NXP Semiconductors MPC5777C - Page 88

CCCR[CCE] can only be set/reset while CCCR[INIT] = 1. CCCR[CCE] is automatically
reset when CCCR[INIT] is reset.
The following registers are reset when CCCR[CCE] is set
• HPMS – High Priority Message Status
• RXF0S – Rx FIFO 0 Status
• RXF1S – Rx FIFO 1 Status
• TXFQS – Tx FIFO/Queue Status
• TXBRP – Tx Buffer Request Pending
• TXBTO – Tx Buffer Transmission Occurred
• TXBCF – Tx Buffer Cancellation Finished
• TXEFS – Tx Event FIFO Status
The Timeout Counter value TOCV[TOC] is preset to the value configured by
TOCC[TOP] when CCCR[CCE] is set.
In addition the state machines of the Tx Handler and Rx Handler are held in idle state
while CCCR[CCE] = 1.
The following registers are only writable while CCCR[CCE] = 0
• TXBAR – Tx Buffer Add Request
• TXBCR – Tx Buffer Cancellation Request
CCCR[TEST] and CCCR[MON] can only be set by the Host while CCCR[INIT] = 1 and
CCCR[CCE] = 1. Both bits may be reset at any time. CCCR[DAR] can only be set/reset
while CCCR[INIT] = 1 and CCCR[CCE] = 1.
3.5.1.2 Normal Operation
Once the M_CAN is initialized and CCCR.INIT is reset to zero, the M_CAN
synchronizes itself to the CAN bus and is ready for communication.
After passing the acceptance filtering, received messages including Message ID and DLC
are stored into a dedicated Rx Buffer or into Rx FIFO 0 or Rx FIFO 1.
Functional Description
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
88 Freescale Semiconductor, Inc.