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NXP Semiconductors MPC5777C - Page 90

NXP Semiconductors MPC5777C
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bit. EDL = recessive signifies a CAN FD frame, EDL = dominant signifies a standard
CAN frame. In a CAN FD frame, the two bits following EDL, r0 and BRS, decide
whether the bit rate inside of this CAN FD frame is switched. A CAN FD bit rate switch
is signified by r0 = dominant and BRS = recessive. The coding of r0 = recessive is
reserved for future expansion of the protocol.
Reception of CAN frames according to ISO 11898-1 is possible in all CAN operation
modes.
The status bits CCCR[FDO] and CCCR[FDBS] indicate the format of transmitted frames.
When CCCR[FDO] is set, frames will be transmitted in CAN FD format with EDL =
recessive. When both CCCR[FDO] and CCCR[FDBS] are set, frames will be transmitted
in CAN FD format with bit rate switching and both bits EDL and BRS = recessive.
In the CAN FD format, the coding of the DLC differs from the standard CAN format.
The DLC codes 0 to 8 have the same coding as in standard CAN, the codes 9 to 15,
which in standard CAN all code a data field of 8 bytes, are coded according to the
following table.
Table 3-58. Coding of DLC in CAN FD
DLC 9 10 11 12 13 14 15
Number of
data bytes
12 16 20 24 32 48 64
In CAN FD frames, the bit timing will be switched inside the frame, after the BRS (Bit
Rate Switch) bit, if this bit is recessive. Before the BRS bit, in the CAN FD arbitration
phase, the standard CAN bit timing is used as defined by the Bit Timing & Prescaler
Register BTP. In the following CAN FD data phase, the fast CAN bit timing is used as
defined by the Fast Bit Timing & Prescaler Register FBTP. The bit timing is switched
back from the fast timing at the CRC delimiter or when an error is detected, whichever
occurs first.
The maximum configurable bit rate in the CAN FD data phase depends on the CAN
clock frequency. Example: with a CAN clock frequency of 20MHz and the shortest
configurable bit time of 4 tq, the bit rate in the data phase is 5 Mbit/s.
In both data frame formats, CAN FD long and CAN FD fast, the value of the bit ESI
(Error Status Indicator) is determined by the transmitter’s error state at the start of the
transmission. If the transmitter is error passive, ESI is transmitted recessive, else it is
transmitted dominant.
Functional Description
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
90 Freescale Semiconductor, Inc.

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