compensation offset is chosen to adjust the secondary sample point inside the bit time
(e.g. half of the bit time in the data phase). The position of the secondary sample point is
rounded down to the next integer number of time quanta tq.
To check for bit errors during the data phase, the delayed transmit data is compared
against the received data at the secondary sample point . If a bit error is detected at the
secondary sample point, the transmitter will react to this bit error at the next following
regular sample point. During arbitration phase the delay compensation is always disabled.
For the transceiver delay compensation the following boundary conditions have to be
considered:
• The sum of the measured delay from M_CAN_Tx to M_CAN_Rx and the configured
transceiver delay compensation offset FBTP[TDCO] has to be less than 3 bit times in
the data phase.
• The sum of the measured delay from M_CAN_Tx to M_CAN_Rx and the configured
transceiver delay compensation offset FBTP[TDCO] has to be less or equal 63
M_CAN clock periods. In case this sum exceeds 63 M_CAN clock periods, the
maximum value of 63 M_CAN clock periods is used for transceiver delay
compensation.
The actual delay compensation value is monitored by reading TEST[TDCV].
3.5.1.4.2 Configuration and Status
Compensation for the transceiver loop delay by the M_CAN is enabled via FBTP.TDC.
The transceiver delay compensation offset is configured via FBTP.TDCO. The actual
delay compensation value applied by the M_CAN’s protocol engine can be read from
TEST.TDCV.
3.5.1.5 Restricted Operation Mode
In Restricted Operation Mode the node is able to receive data and remote frames and to
give acknowledge to valid frames, but it does not send data frames, remote frames, active
error frames, or overload frames. In case of an error condition or overload condition, it
does not send dominant bits, instead it waits for the occurrence of bus idle condition to
resynchronize itself to the CAN communication. The error counters are not incremented.
The Host can set the M_CAN into Restricted Operation mode by setting bit
CCCR[ASM]. The bit can only be set by the Host when both CCCR[CCE] and
CCCR[INIT] are set to 1. The bit can be reset by the Host at any time.
Functional Description
MPC5777C Reference Manual Addendum, Rev. 1, 12/2015
92 Freescale Semiconductor, Inc.
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